725 abbreviations with 1,246 meanings, from the gate and discipline codes on the lifecycle charts to the standards, bodies and industry terms the Hub uses. Where the same letters mean different things, each meaning is listed with the lifecycles that use it. The list is built from the lifecycle and compliance data, so it stays current. For definitions of terms in general, see the glossary.
The partnership that publishes the cellular standards that devices are tested against.
Standards bodies and agenciesStandards and regulations
Used in: 3GPP conformance guide, Interoperability and compliance overlay
A structured eight-step method for solving a quality problem and reporting it to a customer.
Quality and reliability
The software architecture, the hardware-software interface and the security architecture are baselined against the frozen chip specification, so hardware and software teams build to the same interface.
Gate codes
The architecture and the mitigation for each radiation effect are reviewed, with dose budgets and first upset rate predictions showing the requirements can be met.
Gate codes
In: Space lifecycle
The root of trust, boot chain, key management, debug and lifecycle states, isolation and countermeasures are designed, reviewed against the threat model and baselined together with the chip architecture.
Gate codes
The architecture, the safety concept with its diagnostics and fault tolerance, the security architecture and the isolation concept are approved, with a credible estimate that the hardware metrics can be met.
Gate codes
The system architecture and the split of functions between custom silicon, programmable logic, firmware and software are reviewed and baselined, with the interfaces between them under joint change control.
Gate codes
In: System lifecycle
Turns product needs into performance targets and a circuit topology, and decides the budget each part of the circuit gets for noise, power and area.
Discipline codes
In: AMS lifecycle
System, software and hardware architectures are evaluated against agreed criteria, traced to requirements and baselined.
Gate codes
The reference architecture, its variation points and the platform interfaces are reviewed and placed under platform change control, so IP, software and derivative teams build to the same base.
Gate codes
Interviews and evidence review are complete, ratings are consolidated by the assessment team and the first feedback is given.
Gate codes
The cybersecurity case is complete and an independent assessment has judged whether the item achieves an adequate level of cybersecurity.
Gate codes
A full cycle of internal audits, covering every process, shift and site in scope, has been carried out by qualified auditors, and findings have root causes and corrective actions.
Gate codes
In: QMS lifecycle
Designs and sizes the circuit at transistor level: converters, references, regulators, clock generation, sensor front ends and high-speed interface circuits.
Discipline codes
In: AMS lifecycle
Designs the array and the circuits around it: sense amplifiers, word line and bit line drivers, decoders, redundancy and repair, charge pumps and voltage generators, control logic and test modes, for DRAM or NAND.
Discipline codes
In: Memory lifecycle
Measures the circuit on the bench across supply, temperature and process spread, explains the results against simulation and sets the trim and calibration values.
Discipline codes
In: AMS lifecycle
A circuit that turns an analog signal into numbers.
Devices and interfaces
Chooses the process and its device options, such as high-voltage or power devices, and keeps the device models, design kit and custom design flow the circuit designers rely on.
Discipline codes
In: AMS lifecycle
The body that sets the AEC-Q stress test qualifications for automotive components.
Standards bodies and agencies
Used in: AEC-Q guide, Automotive lifecycle: AEC-Q100 Qualification, Automotive lifecycle: AEC-Q100 qualified gate, Interoperability and compliance overlay
The Automotive Electronics Council's family of qualification documents: AEC-Q100 for integrated circuits, AEC-Q101 for discrete semiconductors, AEC-Q104 for multichip modules and AEC-Q200 for passive components, with related guidelines such as AEC-Q001 part average testing and AEC-Q002 statistical yield analysis.
Standards and regulations
Used in: AEC-Q guide
The stress test qualification that integrated circuits pass before use in vehicles.
Standards and regulations
Used in: AEC-Q guide, Automotive lifecycle, Automotive lifecycle: AEC-Q100 Qualification, Automotive lifecycle: AEC-Q100 qualified gate, Interoperability and compliance overlay
The architecture and the interface software sees are baselined.
Gate codes
In: AI accelerator lifecycle, Startup lifecycle, Photonics lifecycle
The radio architecture is chosen and the link budget closes with margin on the candidate technologies: system targets are split into block-level specifications that each have an owner.
Gate codes
In: RF lifecycle
The system architecture, the subsystem breakdown and the interfaces between subsystems are frozen, so subsystem teams can design in parallel against stable specifications.
Gate codes
The logic block, routing architecture, memory and arithmetic blocks, clock network and input and output structure are baselined.
Gate codes
Software that learns from data to classify, predict or generate; on the Hub, also the AI impact notes on each lifecycle.
Devices and interfaces
Used in: AI impact, AI accelerator lifecycle, EU AI Act guide, AI governance overlay
The North American automotive body that publishes APQP, PPAP, FMEA, MSA and SPC manuals.
Standards bodies and agencies
Used in: AIAG and VDA FMEA guide
Agrees the block's interface with the chip it goes into, and delivers it with the views and models the SoC team needs, or as a stand-alone chip or test chip to the foundry.
Discipline codes
In: AMS lifecycle
Firmware, drivers and the board support package are feature complete on models and released as an alpha build for internal teams and bring-up.
Gate codes
Draws the circuit's layout by hand where matching, symmetry and noise isolation matter, and makes it pass the foundry's checks.
Discipline codes
In: AMS lifecycle
Circuits that handle continuous signals, alone or together with digital logic, such as converters and power circuits.
Design and verification
Used in: AMS lifecycle, AMS lifecycle: AMS Specification & Architecture, AMS lifecycle: AMS Verification, AMS lifecycle: AMS specification freeze gate, AMS lifecycle: AMS architecture and specification, AMS lifecycle: AMS verification, and 1 more
Runs corner and Monte Carlo simulation against the specification, builds behavioural models, and checks the circuit together with the digital logic around it.
Discipline codes
In: AMS lifecycle
Develops the test methods for converters, references, regulators, clocks, high-speed interfaces and radios, with trim and calibration, and correlates them with bench measurements.
Discipline codes
Designs the analog, power and interface circuits for dose drift, low dose rate effects where the technology shows them, single-event transients and latch-up, and correlates the simulations with silicon.
Discipline codes
In: Space lifecycle
The certification schemes, assurance levels, regulatory security obligations, export classification and protocol interoperability targets are agreed, with the evidence each one needs.
Gate codes
The architecture and the pin assignment are baselined, so the board can be laid out around them; later changes go through change control.
Gate codes
In: FPGA lifecycle
Owns the business case, the requirements, the datasheet and the customers who sample and design in the product.
Discipline codes
In: AMS lifecycle
Speaks for the converter the device goes into: derives the mission profile and electrical requirements from traction inverters, onboard chargers, industrial drives, renewable energy and data-centre power supplies, estimates losses, builds evaluation boards and reference designs, sets gate drive guidance and supports customers through design-in.
Discipline codes
Turns the benchmark designs into reference designs, builds the development kits, writes the device documentation and supports lead customers through samples and family roll-out.
Discipline codes
The automotive industry's phased method for planning a new product and its production process.
Quality and reliabilityStandards and regulations
Used in: APQP guide, APQP lifecycle, Traceability overlay, APQP lifecycle: APQP program management
The part has passed AEC-Q100 qualification for its temperature grade, with any failure analysed to root cause and closed.
Gate codes
The package, laser attach and fibre attach processes are defined and shown to be capable: coupling loss, alignment stability and yield meet the plan on the builds made so far.
Gate codes
Plans and runs the stress tests that qualify the product, including ESD and latch-up, against the standard its market expects.
Discipline codes
In: AMS lifecycle
A first kit with target device models, a draft design rule manual, basic decks and symbols goes to internal teams and selected partners for design studies and early IP work.
Gate codes
In: PDK lifecycle
Adoption across teams is reviewed against the business case, training records are complete, and the step moves to routine operation under monitoring.
Gate codes
The system, chip and software architectures are reviewed and approved, every risk control measure has a home in the architecture, the means of patient and operator protection are defined, the software safety class is confirmed, and the threat model and security architecture are agreed.
Gate codes
The assessment plan is agreed, the lead assessor is confirmed, and the project can show its real evidence for every process in scope.
Gate codes
Owns the architecture specification and the mitigation architecture: which functions are protected, by which mechanism, and how the part reports, corrects and recovers from radiation events, with the derating rules each block follows.
Discipline codes
In: Space lifecycle
Owns the product and system requirements and the architecture: redundancy, diagnostics, safe states, partitioning between chips, boards and software, and the traceability that ties them to the safety and security requirements.
Discipline codes
Turns product requirements into a chip architecture and a specification the design teams build from.
Discipline codes
In: SoC lifecycle
Turns the application into a link that closes: reach, data rate, wavelength plan, modulation, the link budget and the power and thermal envelope, then tracks the budget to measured silicon and systems.
Discipline codes
Designs the chip architecture with its safety mechanisms, decides how hardware and software share the safety work, and writes the specifications the design, verification and software teams build from.
Discipline codes
Defines the compute units, memory hierarchy, network on chip, chip-to-chip links and the interface software sees, within the power and thermal envelope, and keeps the microarchitecture consistent with them.
Discipline codes
Turns the idea into an architecture that can be built: the model that shows the advantage, the targets and the test chip's content, and checks them against test chip silicon.
Discipline codes
Defines the logic block, routing, memory and arithmetic blocks, clock network and input and output structure, judges them on benchmark designs with the software team, and keeps the device consistent with them.
Discipline codes
Defines the configurable cell, the split between fixed and custom layers, the routing, clock and power networks, the fixed blocks and the array sizes, and judges them by trial mapping of reference customer designs.
Discipline codes
Designs radio circuits such as transceivers, power amplifiers and low-noise amplifiers, where on-chip inductors and interconnect need electromagnetic modelling.
Discipline codes
In: AMS lifecycle
The aircraft and system level development assurance guidance that sits above DO-254 and DO-178C.
Standards and regulations
Used in: ARP4754A guide
The safety assessment methods used beside ARP4754A: the functional hazard assessment, the preliminary system safety assessment and the system safety assessment, supported by fault tree analysis, dependence diagrams, Markov analysis, failure modes and effects analysis and common cause analysis.
Standards and regulations
Used in: ARP4761 guide
A tool is approved to ship to a lead customer for alpha evaluation, with an agreed plan, a joint development agreement, an installation procedure and engineering support in place.
Gate codes
SAE's standard for independent distributors on keeping counterfeit electronic parts out of the supply chain: sourcing, purchasing, inspection and test of parts from outside authorised channels, reporting and quarantine of suspect parts, and records.
Standards and regulations
Used in: AS6081 guide
The aerospace quality management system standard.
Standards and regulations
Used in: AS9100 guide, Interoperability and compliance overlay
Designs the interface ASIC: low-noise front end, conversion, drive and sense loops, references, digital filtering, trim storage and the sensor interface, and evaluates it on silicon with the transducer.
Discipline codes
Performance targets, topology and process options are baselined.
Gate codes
In: AMS lifecycle
A chip designed for one product or task rather than for general use.
Design and verification
Used in: MEMS and sensors lifecycle: Interface ASIC Co-design, MEMS and sensors lifecycle: Interface ASIC tape-out gate, MEMS and sensors lifecycle: First MEMS and ASIC wafers gate, MEMS and sensors lifecycle: Interface ASIC design
The level, A to D, that sets how much rigour a road vehicle safety function needs.
Safety and security
Used in: ISO 26262 guide
Develops and runs the bumping, die attach, bonding and stacking steps that join the dies to the interposer or substrate, and freezes the process for the qualification builds.
Discipline codes
Develops the back-end assembly steps: dicing and singulation, die and chip attach, fine-pitch flip chip, reflow or thermocompression bonding, underfill, moulding, lid and thermal interface attach, ball attach and marking.
Discipline codes
Extracts the layout's parasitics, and checks electromigration, IR drop, ESD protection and latch-up before the block is released.
Discipline codes
In: AMS lifecycle
The interface ASIC is verified by co-simulation with the transducer model across corners and released to the foundry, with its trim architecture and register map fixed.
Gate codes
Plans and runs gap and formal assessments: the scope and plan, the assessment team and its competence, interviews and evidence review, rating and consolidation, feedback, and the report, keeping the independence the assessment class requires.
Discipline codes
The testers that run production test programs on wafers and packaged parts.
Manufacturing, test and packaging
Used in: Test program lifecycle, Test program lifecycle: ATE platform and test operations
The EU rules for equipment used where explosive gas or dust can occur.
Export, trade and product law
Used in: ATEX and IECEx guide
Software that creates the test patterns a tester applies to find manufacturing faults in a chip.
Design and verification
Used in: Test program lifecycle: ATPG and pattern generation
Generates scan patterns for the agreed fault models with compression, memory BIST and logic BIST patterns, reports fault coverage, diagnoses scan failures on silicon and later trims and reorders patterns for test time.
Discipline codes
Before the hardware architecture is committed, the team shows that the process, reused IP, package, tools and libraries are ready for the target automotive grade and mission profile, or records the gaps and how they will close before qualification.
Gate codes
Develops the program that measures analog parameters on every part on a mixed-signal tester, including trim, and sets the production test limits.
Discipline codes
In: AMS lifecycle
Designs and builds the manufacturing execution system, material handling automation, equipment connectivity and data collection to the SEMI equipment communication and carrier handling standards, and the security of the factory's operational technology, then connects every tool and runs the data platform.
Discipline codes
The device or module has been shown working in its target circuit, with reference designs, gate drive guidance and released models ready for customers.
Gate codes
The alpha evaluation shows the tool can meet its key process requirements in a real fab, and the design changes it found are known and planned for the beta build.
Gate codes
Test vehicles show the array yielding on a trend that supports a product die, with the main fail mechanisms understood and repair able to cover what remains.
Gate codes
In: Memory lifecycle
The configurable cell, the split between fixed and custom layers, the routing, the clock and power networks, the fixed blocks and the array sizes are baselined.
Gate codes
The hardware items and executable object code are built from controlled configurations with assessed or qualified tools, integrated on the target hardware, and baselined for formal verification.
Gate codes
Firmware, drivers and the operating system run on silicon, issues are separated into hardware and software, and silicon issues have workarounds or errata entries.
Gate codes
The fab business case is approved and funds site selection and design, with the capital range, financing approach and key assumptions recorded.
Gate codes
Schematics, board layout, the bill of materials and the mechanical and thermal design are reviewed and released for the first prototype build.
Gate codes
In: System lifecycle
Designs the boards the chips sit on: the power tree, schematics, layout, signal and power integrity and the bill of materials, through each prototype build to production data.
Discipline codes
In: System lifecycle
The base array design and the configurable cell library are feature complete.
Gate codes
A beta release that runs on silicon goes to sampling customers with the engineering samples, with its known issues stated.
Gate codes
The structure and building envelope are complete and weathertight, so cleanroom fit-out can start under clean build protocol.
Gate codes
The integrated flow is frozen as the baseline.
Gate codes
The bitstream runs on the product board with its drivers and board support package, and the main functions work end to end.
Gate codes
In: FPGA lifecycle
The array tile, the configurable cells and the fixed blocks, such as memories, clock generators and the input and output ring, are integrated with the clock and power networks in one base array database, and the reference customer designs have been taken through a first trial of the flow on it, with the gaps listed.
Gate codes
The US Department of Commerce agency that administers the Export Administration Regulations.
Export, trade and product law
Used in: Export control overlay
Test logic inside a chip that checks memories or logic without an external tester.
Design and verification
Plans and runs measurements of performance, efficiency and accuracy on the target workloads and public benchmarks, finds the bottlenecks and feeds them to the compiler, library and runtime teams.
Discipline codes
The die-to-die interface and the bump map shared by the dies and the package are baselined, so each die and the package can be designed in parallel.
Gate codes
The list of parts and materials that make up a product.
Business and product lifecycle
Before the production release, the speed, power, temperature and density grades, the test limits that sort parts into them and the use of partly good dies are released and tied to demand, so each orderable part has a grade behind it.
Gate codes
In: Memory lifecycle
Builds the base array layout with its fixed routing, clock and power networks, fixed blocks and input and output ring, closes the physical checks and tapes out the base layers.
Discipline codes
The base array has passed reliability qualification to the chosen standard on test designs, and the rules for qualifying customer devices by similarity to it are agreed.
Gate codes
The first board revision's design is complete and its fabrication and assembly data go to the board manufacturer.
Gate codes
In: FPGA lifecycle
A kit with models fitted to silicon, most rules in place, validated decks, extraction and working PCells lets IP and library teams and early customers start real design work at an agreed risk.
Gate codes
In: PDK lifecycle
A versioned platform baseline is released for reuse: IP catalogue, software, firmware and SDK releases, reference designs, conformance tests and documentation.
Gate codes
Runs the source repositories, the reproducible build, continuous integration and the release process: tagging, packaging, release notes and the archive that lets any shipped version be rebuilt.
Discipline codes
Designs the board around the FPGA: schematics, layout, power supplies, high-speed channels and thermal design, often starting from a reference design.
Discipline codes
In: FPGA lifecycle
The boot ROM code is final and goes into the masks.
Gate codes
Beta tools built close to the production design are approved for shipment to selected customers under evaluation agreements with clear criteria for moving to qualification.
Gate codes
Plans and develops burn-in and system-level test where the strategy uses them: boards, recipes and test content, and their later reduction when the data allows.
Discipline codes
Writes the boot ROM built into the masks: boot source selection, secure boot verification of the first loader, recovery, and the boot flow the later boot stages follow.
Discipline codes
The masks for the fixed base layers are released to manufacture and accepted, with the technology the base depends on confirmed ready.
Gate codes
Plans and runs bring-up of first silicon on its boards with the software stack, validates functions, power and thermal behaviour across conditions, and keeps the errata list.
Discipline codes
Plans and leads the first days and weeks on silicon: the bring-up image, the order in which blocks are brought up, the separation of hardware from software issues, and the errata and workaround list.
Discipline codes
Plans bring-up, brings up first silicon with the configuration logic, security features and hard IP, runs the bring-up designs and keeps the errata list.
Discipline codes
Powers up the first boards, loads the bitstream, and debugs hardware and software together with lab instruments and on-chip logic analysers.
Discipline codes
In: FPGA lifecycle
Banked wafers finished with test designs have been measured, the base array works across voltage and temperature, and the library models have been correlated with silicon.
Gate codes
Plans the test designs that exercise the base, checks the banked wafers, measures finished test designs across corners and qualifies the base array for reliability.
Discipline codes
The base array, its fixed blocks and its cells are verified, and test designs built through the reference flow pass, so the base can be taped out and the design kit released.
Gate codes
Beta tools meet their process, productivity and reliability requirements at several customer sites, with tools matched to each other, and the host interface proven on customer hosts.
Gate codes
The business case is accepted and a team is funded to define the product.
Gate codes
In: Product lifecycle, SoC lifecycle, AMS lifecycle, FPGA lifecycle, Automotive lifecycle, AI accelerator lifecycle, Space lifecycle, Photonics lifecycle, Power and compound lifecycle, RF lifecycle, Medical lifecycle, Industrial lifecycle, System lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
The software scope that the chip's market needs is accepted as part of the product concept, and a software team is funded to define it.
Gate codes
A sensor opportunity is accepted and a team is funded to define what the sensor must measure, for which applications and at what cost.
Gate codes
The security the product's markets expect is accepted as part of the product concept, and a security owner is funded to define it.
Gate codes
The business approves development on the chosen concept, with a business case, a cost of ownership position against alternatives, and a development plan and budget.
Gate codes
The case for a shared platform rather than separate products is accepted, and a team is funded to define it.
Gate codes
Defines the item and its environment, turns the TARA into cybersecurity goals and claims, writes the cybersecurity concept and refines it into an architecture and component specifications.
Discipline codes
Design software in general; in chip teams, also the group that runs the tools, flows and compute.
Design and verification
Used in: AI-assisted flow lifecycle: CAD and flow engineering
Chooses and runs the tools and compute the design needs: the EDA licensing model, cloud or on-premise compute, design kit and library installation, version control, regression, data security and the tape-out archive.
Discipline codes
Owns the flow step: describes the baseline, plans and runs the evaluation and pilot, integrates the qualified step into the controlled flow with its fallback, and releases and updates it.
Discipline codes
The level that sets how much assurance a vehicle cybersecurity measure needs.
Safety and security
Used in: ISO/SAE 21434 guide
Defines the trim architecture with the ASIC team, builds the calibration model, procedure and stimulus equipment, turns them into a production calibration program, and watches calibration residuals and throughput in volume.
Discipline codes
Specifies the control interface and the on-chip and in-system calibration, writes the calibration algorithms and module control software, and locks the regulatory settings in the released software.
Discipline codes
In: RF lifecycle
The original in-vehicle network standard — a multi-master, message-based serial bus that every ECU in a conventional vehicle still uses for low/medium-speed control data, from window switches to engine management.
Standards and regulations
The program and hardware give the same answer on every production tester and hardware set, at every test site, with repeatability and reproducibility within the agreed limits.
Gate codes
The customer has validated the samples in their system against the agreed acceptance criteria and approved the device for production.
Gate codes
The process of fixing the cause of a problem and stopping it from happening again.
Quality and reliability
The FPGA specific primitives have been replaced, the clocks and input and output re-planned, test logic planned, and the converted design shown equivalent to the prototype and agreed with the customer.
Gate codes
Tester results agree with the bench, with simulation and between testers and insertions, within agreed tolerances, so failures seen on the tester can be trusted as failures of the part.
Gate codes
The cell structure and array organisation are chosen, with evidence from simulation and early structures that they can reach the density and the cell behaviour the generation needs.
Gate codes
In: Memory lifecycle
Static, dynamic and ruggedness behaviour is measured across temperature, compared with the design and the target datasheet, and the differences are explained.
Gate codes
Facility systems are commissioned and the cleanroom is certified to its cleanliness class, so tools can be moved in and connected.
Gate codes
The assessment report is issued, the capability profile is compared with the target, and the sponsor and customer agree what follows.
Gate codes
Cybersecurity goals and claims are agreed and the cybersecurity concept allocates requirements to the architecture, the operational environment and suppliers, without unresolved conflicts with safety.
Gate codes
Runs the change process after approval: classification, impact assessment across FMEAs, control plan and approvals, customer notification, requalification tracking, and the end of production and record retention.
Discipline codes
In: APQP lifecycle
The hardware architecture, device technology, component set and software architecture are reviewed and accepted, and the preliminary system safety assessment is updated with the design's fault tolerance and independence.
Gate codes
Designs custom silicon for the device, such as biopotential and sensor analog front ends, stimulation and drive circuits, ultra-low-power processing and power management, with chip-level risk controls, reliability and supply life built into the specification and the design.
Discipline codes
Designs the controllers, isolators, gate drivers, sensor interfaces and power management chips with built-in diagnostics, monitors, redundant channels and secure elements, and supports their analysis and test.
Discipline codes
The customer and the vendor agree the scope, price, engineering charge and schedule for the customer device, which commits development of that device.
Gate codes
Engages early customers and ecosystem partners, certifies tool flows, runs multi-project wafer shuttles and supports customer designs through tape-out and their own product qualification.
Discipline codes
The way accelerators connect within a server and across racks, and the collective communication the software uses, are designed and published as a reference.
Gate codes
The photonic circuit and its drivers and receivers meet their targets in simulation, including co-simulation of the full electro-optic path and the effect of process and temperature variation.
Gate codes
For each customer design, reuses the signed-off base environment to prove the converted design equivalent to the FPGA prototype and the final netlist equivalent to the agreed design, and checks the custom layer tape-out database.
Discipline codes
The certificates or assessment results the plan requires are issued, with any conditions recorded.
Gate codes
Certificates, listings and declarations of conformity are issued for every target market, and the technical file is complete, so the product can be placed on those markets.
Gate codes
The second stage audit is complete, nonconformities are answered and accepted within the time the scheme allows, and the certification body has issued the certificate.
Gate codes
In: QMS lifecycle
Brings customers' workloads into the plan, runs early access, ports and qualifies customer models, writes porting guides and handles field issues for the life of the product.
Discipline codes
Gets customers productive and keeps them so: early-access and beta programs, developer documentation, porting guides, training, issue intake from the field and the migration path at the end of support.
Discipline codes
Assesses each customer design for fit, converts FPGA prototypes to the base array, reviews the design with the customer and supports them until they approve the samples.
Discipline codes
Designs and models the storage cell and the access and peripheral transistors: the structure, the materials, the retention, disturb and endurance behaviour, and the device models the circuit designers use.
Discipline codes
In: Memory lifecycle
Works with system makers and controller and processor vendors: samples and models, interoperability validation with controllers and platforms and interface training margin, each customer's qualification, change and discontinuance notices and their acknowledgement.
Discipline codes
In: Memory lifecycle
The company exists as a legal entity with its founders, their roles, equity and decision rights agreed in writing, and the inventions it will build on assigned to it, so it can sign agreements and take investment.
Gate codes
The configuration memory, the configuration controller, the bitstream format and the security features are baselined, so the tiles, the software and the bitstream generator can be built against them.
Gate codes
Designs the configuration memory and controller, the bitstream format, partial reconfiguration where offered, error detection in the configuration memory, and the encryption, authentication, key storage and tamper response that protect customers' designs.
Discipline codes
Formal conformance and regulatory testing has passed for each target market, and the certifications, declarations and reports needed to sell there are issued or filed.
Gate codes
In: RF lifecycle
Owns the cybersecurity management system: policy, governance, roles, processes, competence, organisational audits, the cybersecurity plan of each project, independent assessment and the archive of records.
Discipline codes
Measures the fabric and the hard IP across voltage, temperature and process, turns the measurements into timing model data, and sets the speed and temperature grades with their guard bands.
Discipline codes
Characterises the libraries for timing, power and noise at the agreed corners on each model release, generates and checks their views, and runs library QA before each library release.
Discipline codes
In: PDK lifecycle
Plans and runs characterisation across corner lots, voltage and temperature, sets test limits and guard bands from the data, and later supplies the data that justifies removing or sampling tests.
Discipline codes
Measures the devices: static characteristics, capacitances and gate charge, double pulse switching, body diode and reverse recovery, avalanche and short-circuit ruggedness, threshold stability and dynamic on-resistance for gallium nitride, across temperature, and repeats the comparison for larger wafers and in the target circuit.
Discipline codes
Plans the measurements, designs evaluation boards and fixtures, calibrates the bench, measures S-parameters, noise, linearity, power and spectral performance with de-embedding, and writes the characterisation report and datasheet values.
Discipline codes
In: RF lifecycle
Finds lead customers, turns their product needs into shared requirements, runs the joint development agreement and its reviews, supports customer designs and sample builds, and secures the customer's approval for volume.
Discipline codes
Designs the low-noise amplifiers, mixers, power amplifiers, switches, oscillators, synthesisers, phase shifters and filters, using electromagnetic models of the passives, and closes post-layout performance.
Discipline codes
In: RF lifecycle
Every component the circuit uses is available in a released kit or library, with compact models fitted to measured data, and each custom component has a plan and a test structure.
Gate codes
The calibration model, procedure and stimulus equipment are approved, and calibrated parts meet the accuracy targets across temperature with the residuals understood.
Gate codes
The organisation's cybersecurity management system is in place, audited and able to support projects; for a vehicle maker it is ready for, or holds, a certificate of compliance under UN R155.
Gate codes
Owns the configuration management plans, baselines, problem reporting, change control, the environment and configuration indexes and the archive, so that any delivered item can be traced to, and rebuilt from, its data.
Discipline codes
Identifies configuration items, controls their versions, branches and baselines, records and tracks every problem to closure, and runs change requests through analysis, approval, implementation and confirmation.
Discipline codes
Keeps the platform baselines, versions and change control, assembles each platform release, audits derivatives against it, and archives the platform at its end.
Discipline codes
Allocates banked wafers to each customer design, orders its custom masks, finishes and packages its wafers, and plans the bank and capacity for the device through to the last builds.
Discipline codes
The mainstream transistor technology for logic and most chips.
Devices and interfaces
Polishing a wafer flat between process steps.
Manufacturing, test and packaging
Lists the sensor interface, automotive, medical, environmental and materials standards the sensor must meet, plans and records interface conformance testing, and issues the materials declarations, export classification and other evidence customers ask for.
Discipline codes
Plans certification for every target market and scheme, runs pre-compliance scans, manages formal testing at accredited laboratories, and keeps the certification file and its change assessments current.
Discipline codes
In: RF lifecycle
Works out which approvals each market needs, plans them from the start, runs pre-compliance and formal tests with accredited laboratories, and holds the certificates and declarations of conformity.
Discipline codes
In: System lifecycle
Builds the compiler that turns models from machine learning frameworks into programs for the accelerator: graph optimisation, operator fusion, tiling, memory planning, scheduling and code generation, with autotuning and quantisation tools.
Discipline codes
The core technical claim has been shown in simulation and on an FPGA prototype or emulator with representative workloads, and the results are written up so investors, partners and new hires can check them.
Gate codes
The item is defined and the project's cybersecurity activities are planned, tailored and staffed, with reuse and off-the-shelf decisions recorded.
Gate codes
Runs the relationship with evaluation and qualification customers: lead customer and joint development agreements, alpha and beta evaluation plans and reports, customer qualification, acceptance and the service agreements that follow.
Discipline codes
Owns the business case, the cost model across dies, package, assembly and test, the relationship with any third-party chiplet suppliers, and the plan with lead customers through sampling to production release.
Discipline codes
The general-purpose processor that runs a system's main software.
Devices and interfaces
Lead customers have qualified the part in their own products, by their own tests or a production part approval where their market asks for one, and approve it for their production, or have agreed when they will.
Gate codes
The die, package and stack pass their qualification to the published JEDEC methods and the target application, and the result is recorded.
Gate codes
In: Memory lifecycle
A cost or improvement change, such as a die shrink, a new material source or an assembly change, has been qualified and notified to customers, and is ready to implement.
Gate codes
At least one lead customer product built on the technology passes the customer's qualification and system evaluation, and the customer approves it for volume.
Gate codes
Owns the relationship with the customer's quality organisation: captures the voice of the customer and every customer specific requirement, prepares and submits the PPAP, handles customer portals, scorecards, complaints and change notifications.
Discipline codes
Plans and runs each customer device's qualification, largely by similarity to the base array family, then watches its field quality and handles change notifications to the end of life.
Discipline codes
Chooses the algorithms, key sizes and random number generation, designs the cryptographic accelerators and key management, and builds in and assesses the countermeasures against side-channel and fault injection attacks.
Discipline codes
Samples of the revision that carries the fixes from lead customer feedback are released to the wider customer base, with an updated datasheet, the current errata and the evaluation kit, so more customers can evaluate and design in the part before it is qualified.
Gate codes
Characterised parts with a preliminary datasheet and known limits go to lead customers for evaluation.
Gate codes
The device architecture and the main module options are chosen, with evidence from simulation and short experiments that they can work together.
Gate codes
The transduction principle, the structure and the process route are chosen together, with multiphysics evidence that the concept can meet the error budget.
Gate codes
One package structure is chosen from the options studied, with modelling evidence that it can meet the electrical, thermal, mechanical and cost targets, and the remaining gaps are named.
Gate codes
Timing, physical checks, test coverage and equivalence are clean on the design placed and routed on the fixed base, and the customer has signed off the final design.
Gate codes
Answers customer questions and escalations after launch, keeps the support knowledge base and order fulfilment working, and carries the support and warranty obligations past the last shipment.
Discipline codes
Gives customers what they need to use the product securely: the secure integration guide, provisioning and key handling support, security notices and migration guidance at the end of support.
Discipline codes
Builds security into the device under IEC 81001-5-1 and the security expectations of the target markets: threat modelling, security architecture, secure boot and update, security testing, the security risk report, vulnerability monitoring and coordinated disclosure.
Discipline codes
Owns the electronic component management plan, component selection and qualification, counterfeit parts avoidance to AS5553 and AS6081, supplier control, export classification and the obsolescence plan through to the last-time buy.
Discipline codes
Where the cybersecurity plug-in is in scope, derives cybersecurity requirements from the threat analysis and risk assessment, designs them into the architecture, implements and verifies them, and keeps cybersecurity risk management and supplier cybersecurity in step with the engineering processes.
Discipline codes
Chooses the chips, FPGAs and modules the system uses, writes the requirements for any custom chip and follows it through its own lifecycle, and brings the suppliers' design-in material and errata into the system design.
Discipline codes
In: System lifecycle
Runs the cybersecurity work under ISO/SAE 21434 alongside the safety work: threat analysis and risk assessment, cybersecurity requirements, security verification and the cybersecurity case.
Discipline codes
A vehicle maker's organisation-wide system for managing cybersecurity risk, needed for type approval.
Safety and security
Used in: UN R155 guide, Vehicle cybersecurity lifecycle: CSMS mandate approved gate, Vehicle cybersecurity lifecycle: CSMS established gate
The control software can run the integrated tool safely, with interlocks verified, recipes and alarms working, and the factory host interface implemented to the agreed public standards.
Gate codes
Formal certification tests for the target markets are passed, at accredited laboratories where required, and the test reports are complete.
Gate codes
In: System lifecycle
Plans which certification schemes and assessments the product needs, prepares the security target and evidence, works with the evaluation laboratory and keeps the certificates valid through product changes.
Discipline codes
Defines the competence each role affecting quality needs, trains and qualifies people, including internal auditors and core tools users, keeps the competence matrix and checks awareness of the policy and objectives.
Discipline codes
In: QMS lifecycle
Plans test for each customer design on the platform test architecture, inserts and checks test in its netlist, and develops the sample and production test programs.
Discipline codes
Lead system makers have validated the part on their platforms and approved it for their products.
Gate codes
In: Memory lifecycle
Finds out what customers actually need, recruits design partners, supports their evaluations and turns their results into product requirements, purchase orders and a pipeline of design wins.
Discipline codes
Verifies custom chips against their specification and chip risk control requirements, with mixed-signal and fault injection verification of the safety mechanisms the device relies on, and feeds failure modes to the device risk analysis.
Discipline codes
The public catalogue of disclosed vulnerabilities, each with its own identifier.
Safety and security
Used in: Security overlay
The public list of software and hardware weakness types that lead to vulnerabilities.
Safety and security
Used in: Security overlay
A cache-coherent interconnect built on the PCI Express physical layer, used to share memory between devices.
Devices and interfaces
Defines and designs the links between dies, usually to an open die-to-die standard, including their test and lane repair features, signs off their timing and checks interoperability.
Discipline codes
The design database, verification and test data, the production test program and the qualification records are archived, so later questions from customers or the field can still be answered.
Gate codes
In: SoC lifecycle
The design team and the test team agree the test features the chip carries and how each one will be used on the tester, so the design can be built to be testable at the cost the plan allows.
Gate codes
Security, legal and the business owner approve the data flows, storage, retention, training rights, output ownership, licence terms and export position for production use, and the supplier agreement reflects them.
Gate codes
The functions, failure conditions and their classifications are agreed with the system integrator, and every hardware and software item has a development assurance level with its rationale.
Gate codes
The cybersecurity architecture and component specifications are complete and verified against the concept, and supplier requirements are flowed down.
Gate codes
A new product derived from the platform is approved: its market, its configuration of the platform, what it adds and its business case.
Gate codes
Designs how debug and test access is authenticated and locked across the device lifecycle states, so scan, test modes and debug ports cannot be used to reach secrets in the field.
Discipline codes
The level, A to E, that sets how much assurance airborne hardware or software needs.
Safety and security
Used in: DO-254 guide
All planned logic is written, integrated and reviewed.
Gate codes
In: FPGA lifecycle
When a fab or area closes, tools are removed or transferred, systems are decontaminated, the site is remediated and permits and agreements are closed.
Gate codes
The business commits the investment in MEMS process, ASIC, package, calibration and qualification, against an agreed development plan, cost target and reliability requirements.
Gate codes
The derivative's configuration and new content are verified against the platform rules: the conformance tests pass, and every deviation from the platform is recorded and approved.
Gate codes
Controls documents and records: approval, versions, distribution, access, retention and disposal, the quality manual or system description, and the change management that keeps documents in step with processes.
Discipline codes
In: QMS lifecycle
The business decides to discontinue the product, with the customer base, contractual commitments, migration path and final supply plan reviewed before any notice goes out.
Gate codes
Each die's design is complete, through its own sign-off and frozen against the shared interface and bump map, and cross-die verification runs on the frozen designs towards the multi-die sign-off.
Gate codes
The cell structure, drift layer, edge termination, gate design and layout are fixed and the masks can be ordered; later changes go through change control.
Gate codes
Plans retention and deletion of data the step touches, builds the provenance and logging scheme that marks AI-assisted results with their versions, keeps the usage and override log, and archives the records at retirement.
Discipline codes
The family of memory interfaces that move data on both edges of the clock.
Devices and interfaces
The current mainstream system-memory generation, doubling DDR4's peak bandwidth and moving power regulation onto the DIMM itself (PMIC) for tighter per-module voltage control.
Standards and regulations
Writes the user guide and release documents, packages each release with its installation checks, delivers it securely to entitled users, and keeps the archive of every version.
Discipline codes
In: PDK lifecycle
Sets the device targets, simulates devices with TCAD, characterises them on silicon and builds the compact device models the design kit carries.
Discipline codes
Designs the power device: cell and channel structure, drift layer, edge termination, gate and source layout, current sharing across a large die and the trade between on-resistance, switching loss, short-circuit withstand and gate oxide field, using TCAD and layout tools, then correlates the design with silicon and feeds ruggedness findings back.
Discipline codes
The RTL and analog design are complete with mitigation in place, reviewed against the mitigation architecture and the derating rules, and further changes go through change control.
Gate codes
In: Space lifecycle
The basis of design and the detailed design are frozen and released for construction; later changes go through change control with their cost and schedule effect stated.
Gate codes
Chip and board designs are complete and frozen for verification and type test builds; later changes go through change control with an impact analysis on safety, security and certification.
Gate codes
The hardware design, enclosure and main software features are frozen for the design validation build, and the technology the system depends on is confirmed ready.
Gate codes
In: System lifecycle
The customer design has been assessed: the array size, the memories, clocks and input and output it needs, the timing it can reach and the conversion work it needs are agreed with the customer.
Gate codes
A safety analysis that looks for single causes, such as shared supplies or clocks, that could defeat redundant parts at once.
Safety and security
Used in: Automotive lifecycle: Safety Analyses: FMEDA, FTA & DFA
Design practices and checks that make a layout easier to manufacture with good yield.
Design and verification
Used in: PDK lifecycle: DFM Rules & Fill, PDK lifecycle: DFM rules and fill released gate, PDK lifecycle: DFM rules and fill
Recommended rules, lithography hotspot checks and fill decks are released and checked on real layouts, so designs on the kit can be made more robust before tape-out.
Gate codes
In: PDK lifecycle
Adds the yield protection beyond minimum rules: recommended rules, lithography hotspot checks, critical area guidance and fill decks.
Discipline codes
In: PDK lifecycle
Structures added to a chip, such as scan chains and built-in self test, so it can be tested after manufacture.
Design and verification
Used in: SoC lifecycle: Full-Chip DFT, SoC lifecycle: DFT insertion sign-off gate, Soft IP lifecycle: IP DFT & Implementation Views, Automotive lifecycle: DFT and in-system test, Test program lifecycle: Test Strategy & DFT Alignment, Test program lifecycle: DFT architecture aligned gate, and 5 more
Adds and connects the full-chip test structures, such as scan chains and built-in self-test, around each IP block's own, so every manufactured chip can be tested.
Discipline codes
In: SoC lifecycle
Designs test access for production test and for in-system tests the chip runs in the vehicle, such as logic and memory built-in self-test at start-up and during operation, and generates the test patterns.
Discipline codes
Agrees with the chip design team the test features the chip carries (scan, compression, memory BIST, logic BIST, boundary scan, IEEE 1500 wrappers and IEEE 1687 instruments) and describes how the tester reaches each one.
Discipline codes
A customer has chosen the part for a program on the evidence of the reference designs, models and samples, and agreed the qualification and approval steps, the customer-specific requirements and the supply expectations.
Gate codes
Design input requirements are complete, unambiguous, verifiable and traced to user needs, essential performance and basic safety are defined, the first hazard analysis and use specification exist, and a design review has approved the inputs.
Gate codes
Designs each die to the shared interface and bump map, including memory stacks and photonic dies where the product uses them, hands the package team the views it needs, and signs off and releases each die.
Discipline codes
The cell library, timing models, custom layer rules and reference flow are released, so customer designs can be assessed and implemented while the base is being built.
Gate codes
A versioned package design kit, with assembly design rules, models correlated to qualified hardware, libraries, checking decks and reference designs, is released to lead customers for product designs.
Gate codes
State what the design teams need from the step, judge pilot outputs as the owners of the work, update design review checklists and lead the first live project's use of the step.
Discipline codes
The design is frozen and the layout is complete; from here only fixes found by sign-off and verification are accepted, each one reviewed.
Gate codes
Customers and channel partners receive a formal notice that the product will be discontinued, with the last-time-buy and last-time-ship dates and any replacement.
Gate codes
In: Product lifecycle, Memory lifecycle, MEMS and sensors lifecycle, System lifecycle
Customers are told the node will be withdrawn, with the last order and last wafer start dates, in line with their agreements and published notice practice such as JEDEC JESD48.
Gate codes
Customers are told formally that the package technology will be withdrawn, with the last order and last shipment dates and the migration options.
Gate codes
The guidance aviation authorities recognise for airborne software.
Standards and regulations
Used in: DO-178C guide, Traceability overlay
The guidance aviation authorities recognise for showing that complex airborne electronic hardware, above all FPGAs, other programmable devices and custom ASICs, was developed with enough rigour for its assurance level.
Standards and regulations
Used in: DO-254 guide, Functional safety overlay, Traceability overlay
Guidance on qualifying the tools used in airborne software and hardware development when their output is not otherwise verified.
Standards and regulations
Used in: Traceability overlay, AI governance overlay
The design and development plan, risk management plan, software development plan and quality plan are approved, responsibilities and review points are set, and the design history file is opened so every later output has a place under document control.
Gate codes
At least one potential customer has signed an evaluation or joint development agreement, with what they will evaluate, how success is judged and what each side commits.
Gate codes
The device has passed its qualification stresses and ruggedness tests to the chosen standard, such as AEC-Q101 or JEDEC, and the lifetime model supports the mission profile.
Gate codes
Every engineering lifecycle in the product has signed off its part and released it for manufacture, such as a SoC tape-out, an analog block hand-off or an FPGA bitstream with its board, and the business is ready to build, validate and sample.
Gate codes
Schematic-level design is complete with electromagnetic models of every critical passive in the simulation, and the circuits meet their block specifications across corners before layout is committed.
Gate codes
In: RF lifecycle
The security blocks and the boot and security code are implemented, and an independent secure design review has found no open high-severity issue.
Gate codes
The detailed hardware design and the software low-level requirements and source code are complete for the baseline, reviewed against their standards, traced, and ready for implementation; the design review with the certification authority, where held, has its findings recorded.
Gate codes
Every process of the system is defined with an owner and measures, and the documented information is released under control so implementation can be measured against it.
Gate codes
In: QMS lifecycle
The derivative product is released for production through its own chip and product lifecycles, on a named platform version.
Gate codes
The device configures from each supported source, encrypted and authenticated bitstreams load, the bring-up designs run with correct results, every hard IP block has been brought up, and differences from the design are listed as errata.
Gate codes
Writes the operating system drivers for the chip's blocks and the board support package that brings an operating system up on the reference boards, and carries them across new operating system versions.
Discipline codes
The main working memory of computers, which stores bits as charge that must be refreshed.
Devices and interfaces
A check that a layout follows the foundry's geometric rules.
Design and verification
Writes and maintains the design rule manual: every layer and device rule, its intent and its drawings, from the process team's rule intent and silicon learning.
Discipline codes
In: PDK lifecycle
The test structures are in the full-chip netlist and the test patterns reach the coverage the test plan asks for.
Gate codes
In: SoC lifecycle
The FPGA family and device are chosen, with headroom for the design's logic, memory and I/O, and with their availability checked.
Gate codes
In: FPGA lifecycle
A design kit with models fitted to early silicon and most rules in place lets IP and library teams, and early customers, start real design work at an agreed risk.
Gate codes
Processing of sampled signals in digital logic or on a processor built for it.
Devices and interfaces
Takes a new product from the released platform: proposes its configuration, reuses what it can, records any deviation, and carries it into its own chip and product lifecycles.
Discipline codes
Tuning the process and the design rules together so a new node gives the expected gains.
Design and verificationDiscipline codes
Every coded rule in the design rule check, layout versus schematic, antenna, density and electrical rule decks has been run on layouts written to pass and to fail it, in each supported tool category.
Gate codes
In: PDK lifecycle
Units built close to production pass functional, performance, power, thermal, environmental, reliability, software and security testing against the requirements, with any differences recorded and dispositioned.
Gate codes
In: System lifecycle
The first parts have been tested against the customer device specification across voltage and temperature, with any differences listed.
Gate codes
Proves the full chip does what the specification says, through simulation, emulation, formal methods and coverage, relying on each IP block's own verification.
Discipline codes
In: SoC lifecycle
Plans and runs simulation, formal checks and performance verification, and builds the emulation platform on which the software stack runs real workloads before tape-out.
Discipline codes
Writes and verifies the RTL for the test chip's reduced scope, builds the verification environment the product reuses, and roots out the cause of issues found on test chip silicon.
Discipline codes
Verifies the fabric, the configuration logic, the security features and the hard IP connections, including simulation of the device model programmed with bitstreams from the vendor's own software.
Discipline codes
Verifies the base array, its cells and fixed blocks, and test designs through the reference flow, and builds the environment that each customer design reuses.
Discipline codes
Verifies the die against its specification and the interface standard: behavioural models of the array and control logic, command and timing checks, mixed-signal checks of the analog periphery, error correction and repair, and the models customers and controller designers use.
Discipline codes
In: Memory lifecycle
Lead customer feedback is reviewed, agreed changes are under change control, and the design win pipeline is good enough to plan launch and volume.
Gate codes
An early drop goes to SoC teams so they can start integration and floorplanning, with its limits stated.
Gate codes
Lead customers receive early access systems and software, with known limits and errata documented.
Gate codes
A first design kit with target device models and draft rules goes to internal teams and selected partners for design studies and early IP work, with its limits stated.
Gate codes
The SDK, toolchain and reference software are released to early-access customers, with their limits stated, so customers can start their own software while silicon is brought up.
Gate codes
The depth of a Common Criteria security evaluation.
Safety and security
Used in: Common Criteria guide
The US rules for exporting dual-use and many commercial items, software and technology.
Export, trade and product lawStandards and regulations
Used in: ITAR and EAR guide, Export control overlay, Interoperability and compliance overlay
The class for items subject to US export rules that are not on a specific control list entry.
Export, trade and product law
Used in: ITAR and EAR guide
Extracted resistance and capacitance agree with measurements on interconnect test structures within the accuracy targets set in the plan, and the electromigration rules are drafted.
Gate codes
In: PDK lifecycle
The part and its technology have a first export classification, and a technology control plan says who may see the design data and where it may go.
Gate codes
In: Space lifecycle
Before any tool, part, software or technical data leaves for a customer, the tool and its technology are classified under the export rules that apply and any licences needed for the first shipments are held.
Gate codes
Designs the tool's electrical systems: power distribution, RF and high-voltage supplies, motion and robot control hardware, sensors and input and output, safety circuits and interlocks, cabling and electrical drawings.
Discipline codes
The code that places an item on the US Commerce Control List and sets which licences apply.
Export, trade and product law
Used in: Export control overlay
Leadership decides whether to expand the fab, convert it to a new technology, sell it or wind it down, on a business case that covers customers, people, permits and incentive terms.
Gate codes
The software tools used to design, simulate, verify and lay out chips.
Design and verification
Used in: Tool and flow decisions, PDK lifecycle: EDA tool and reference flow enablement, Startup lifecycle: EDA, compute and design infrastructure
Agrees which tool categories and versions the kit supports, ports decks and technology files to each, and certifies the reference design flows customers use on the node.
Discipline codes
In: PDK lifecycle
Sets the site environmental baseline, leads the environmental impact assessment, sets sustainability targets for energy, water, emissions and waste, reviews designs for hazards, readies hazardous materials systems, signs off tool safety against SEMI S2 evaluations and reports emissions, discharges and performance to the authorities.
Discipline codes
The engineering validation build is assembled and brought up: boards, chips, firmware and software work together end to end, and the design issues found are fixed or planned for the next build.
Gate codes
In: System lifecycle
Designs the electronic circuits the optics depend on: modulator drivers, transimpedance amplifiers, the interface to the host SerDes, heater and bias control, monitoring and the control firmware, on the photonic die or a separate electronic die.
Discipline codes
In RF design, the field effects of a layout that are modelled and extracted to check performance.
Design and verification
Used in: RF lifecycle: Layout & EM Extraction, RF lifecycle: Circuit and EM design review gate
Engineering models, electrically representative but not screened or qualified for flight, are released to customers so they can start board and system work.
Gate codes
In: Space lifecycle
Builds and validates electromagnetic models of inductors, transformers, baluns, transmission lines, pads and package transitions, runs full electromagnetic extraction on the layout, and correlates the models with measured structures.
Discipline codes
In: RF lifecycle
A product's ability to work without causing or suffering from electromagnetic interference.
Quality and reliability
Used in: Medical lifecycle: Design Verification: Function, Electrical Safety & EMC, Medical lifecycle: Electrical safety and EMC tests passed gate, Medical lifecycle: Electrical safety, EMC and compliance testing, Industrial lifecycle: EMC, safety and environmental testing, Interoperability and compliance overlay
Runs the full-chip RTL on an emulator from the first stable RTL drops until tape-out, so long tests and real software run before silicon.
Discipline codes
In: SoC lifecycle
Customers are told when security support will end, what the final update will contain and where to move.
Gate codes
Customers and partners are told when cybersecurity support for the item or vehicle type will end and what that means for them.
Gate codes
The umbrella standard for railway RAMS.
Standards and regulations
Used in: EN 50126 guide
The railway standard for developing, verifying, validating, assessing and maintaining software in control and protection systems such as interlocking and train protection.
Standards and regulations
Used in: EN 50128 guide
The railway standard for the safety case of electronic signalling systems, subsystems and equipment.
Standards and regulations
Used in: EN 50129 guide, Functional safety overlay
The newer single railway software standard, covering signalling, rolling stock and fixed installations.
Standards and regulations
Used in: EN 50716 guide
Commits engineering capacity and technical direction, judges feasibility, owns the engineering lifecycles that run inside development, and signs off that the design is ready to release, sample, qualify and sustain.
Discipline codes
The final security update and advisory are released, keys and certificates are retired and the records are archived.
Gate codes
Cybersecurity support has ended: final updates and advisories are out, keys and back-end services are retired or handed over, decommissioning guidance is published and records are archived.
Gate codes
The point at which a product is discontinued and no longer made or supported.
Business and product lifecycle
Used in: Obsolescence overlay, Product lifecycle: Post-EOL Support
The final quantities have shipped and the part is no longer made or sold.
Gate codes
In: SoC lifecycle, Photonics lifecycle, RF lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
Users are told which kit versions will stop being supported and when, with the version or node to move to, in line with their agreements and the node's own discontinuance notice.
Gate codes
In: PDK lifecycle
Warranty, support and record-keeping obligations are met or handed on, and the product's records are closed.
Gate codes
In: Product lifecycle, Hard IP lifecycle, AI accelerator lifecycle
The last parts have shipped, and records, samples and field monitoring obligations are handed to their long-term owners.
Gate codes
The decision to end support for a platform is announced to customers with the last order dates for tools and spares, the final support date and any transfer of support.
Gate codes
The product's discontinuance is announced and the test plan for the last-time buy is agreed: capacity, hardware spares and the final test runs.
Gate codes
The candidates to evaluate, the reference designs with known answers and the success criteria are fixed before any result is seen, so the pilot cannot be judged on what it happened to do well.
Gate codes
Series supply of the part has ended as notified: last-time-buy orders are shipped, any service supply is in place, and records are retained for the agreed period.
Gate codes
In: APQP lifecycle
Runs the design at speed on emulators and FPGA prototypes before the final hardware exists, so firmware and software can be brought up and hardware and software verified together.
Discipline codes
Every tool the flow needs is selected, installed, accepted and matched, and its capability is shown on product-like material, so the pilot line can run.
Gate codes
Owns the equipment qualification plan, environmental and electromagnetic qualification testing, reliability prediction and derating, and the compliance evidence the equipment specification and any technical standard order call for.
Discipline codes
Specifies, evaluates, selects, installs and qualifies the bonders, plating, deposition, lithography, grinding, dicing, inspection and metrology tools, matches tools that run the same step, and plans tool capacity for the ramp.
Discipline codes
Works with equipment and materials suppliers so that each new tool, chemical, gas and substrate is ready, qualified and in supply when the node needs it, and stays in supply to the end of its life.
Discipline codes
The program is good enough to screen engineering samples: it catches the known failures, its coverage gaps are listed, and samples can ship with the test limits stated.
Gate codes
Validated early parts go to lead customers for evaluation and design-in, with known issues documented and the agreements and export checks for sample shipments in place.
Gate codes
In: Product lifecycle, SoC lifecycle, Chiplet lifecycle, Automotive lifecycle, Memory lifecycle, Photonics lifecycle, Power and compound lifecycle, MEMS and sensors lifecycle, RF lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
Builds from last-time-buy stock have ended, the final field update and security advisory are published, and repairs and support end as announced, with the design, bitstream sources and build environment archived.
Gate codes
In: FPGA lifecycle, Medical lifecycle, Avionics lifecycle, Industrial lifecycle, System lifecycle
The final release and final security advisory have shipped, the source, build environments and signing records are archived, and support closes.
Gate codes
The final lots are built, screened and shipped, and every record the missions may need is archived.
Gate codes
In: Space lifecycle
The security target and the evaluation evidence package are complete and handed to the evaluation laboratory or assessor.
Gate codes
Maintenance and security releases for the platform end as announced, and its IP, software, tools and records are archived.
Gate codes
Helps derivative teams and customers use the platform: documentation, training, support handovers, usage metrics and migration guidance when the platform retires.
Discipline codes
A sudden static discharge that can damage a chip; chips carry protection circuits and are tested for it.
Manufacturing, test and packaging
Used in: AMS lifecycle: Extraction, reliability and ESD checks
The sustainability and governance matters companies report on.
Business and product lifecycle
Plans and runs type testing for basic safety and essential performance to IEC 60601-1 with its collateral and particular standards, EMC to IEC 60601-1-2, and the radio, battery and other product compliance tests the markets need, usually with an accredited laboratory.
Discipline codes
Models signal and power integrity, heat flow, warpage, stress and solder joint fatigue for each concept and test vehicle, correlates the models with measured hardware, and delivers the models that go into the design kit.
Discipline codes
The law that governs placing medical devices on the EU market.
Standards and regulations
Used in: EU MDR guide
Lithography with very short wavelength light, used to print the finest features of leading-edge nodes.
Manufacturing, test and packaging
A preliminary abstract, pin list and timing model go to SoC teams so they can floorplan around the macro, with their limits stated.
Gate codes
Attacks the silicon and its software as a capable attacker would: penetration tests, side-channel and fault attacks, protocol interoperability and conformance tests, and reproduction of reported vulnerabilities.
Discipline codes
Classifies the part and its technical data under the export rules that apply, such as ITAR or the EAR with its ECCN, writes and runs the technology control plan, obtains licences or other authorisations, screens every party and destination, and keeps the records the rules require.
Discipline codes
In: Space lifecycle
The first units are assembled and their build is reviewed for bonding, alignment and warpage problems.
Gate codes
The first production unit has passed first article inspection to AS9102 against the released design data, on the production line, with production test procedures released.
Gate codes
The independent functional safety assessment judges that the product and its development meet the target integrity level, and the safety case and safety manual are released.
Gate codes
Works with the foundry on the process, the masks and wafer fabrication.
Discipline codes
In: SoC lifecycle
Chooses the photonic foundry and platform, books shuttle or dedicated runs, follows the wafers through the fab with their process control data, and plans wafer capacity for volume.
Discipline codes
Runs the device wafers in production: line readiness, statistical process control, defect inspection and excursion response, yield learning against material and process defects, the larger-wafer line and continuous improvement once in volume.
Discipline codes
An engineer who helps customers design a company's chips into their products.
Business and product lifecycle
The technical bridge to customers: brings their use cases into the definition, builds evaluation kits, reference designs and application notes, supports design-in, and helps customers migrate at end of life.
Discipline codes
Owns the business case, the family requirements and roadmap, the benchmark designs that stand for customers' work, the order in which members are released, the launch and sample programme and the discontinuance.
Discipline codes
First silicon arrives from the SoC lifecycle and boots on the reference board through the boot ROM to the first loader, starting software bring-up.
Gate codes
The accomplishment summaries and configuration indexes are accepted, the item conforms to its data, open problem reports are agreed, and the final stage of involvement closes the compliance findings.
Gate codes
The team, with management, commits that the part can be made, measured, tested and packed in the required volume and quality at acceptable cost, or records what must change first.
Gate codes
In: APQP lifecycle
The US regulator whose rules cover radio frequency devices and their emissions.
Standards bodies and agencies
Supports customers who integrate the product into safety systems, machinery and plants, collects field failures and returns, and feeds field data back into the FMEDA, the safety case and the next design.
Discipline codes
The US regulator of medical devices, among other products.
Standards bodies and agencies
Used in: FDA design controls guide
Develops the site master plan, concept and basis of design, detailed design and construction cost estimate, then manages construction of the structure, envelope and cleanroom fit-out to the design, and keeps as-built records.
Discipline codes
Plans and runs simulation, clock domain crossing and lint checks so that problems are found before the slower debug on hardware.
Discipline codes
In: FPGA lifecycle
The step runs inside the controlled flow with locked versions, logging of AI-assisted results, access controls, a passing regression suite and a tested fallback to the conventional step.
Gate codes
Functional verification is complete and fault injection campaigns show that the mitigation behaves as the architecture claims, with any unprotected sensitivity explained and accepted.
Gate codes
In: Space lifecycle
The full capital for construction and the first phase of tools is committed, on a design, cost estimate, schedule, permit and incentive position that leadership has accepted.
Gate codes
Builds and maintains the financial model, sets cost and price targets with product management, tracks the development budget, standard cost and margin, and judges the financial effect of lifecycle decisions.
Discipline codes
Keeps the money in step with the evidence: the financial model and runway, grants, each funding round, the data room and the cap table, and the board and investor reporting that follow each round.
Discipline codes
Develops, characterises and silicon-validates the standard cell libraries, memory compilers and I/O libraries that almost every design on the node needs.
Discipline codes
Designs the foundation IP that ships with the kit: standard cell libraries in the chosen cell architectures and threshold voltage options, IO libraries and memory compilers, with their layouts, abstracts and netlists.
Discipline codes
In: PDK lifecycle
The US federal standard for cryptographic modules, aligned with ISO/IEC 19790 and tested using ISO/IEC 24759.
Standards and regulations
Used in: FIPS 140-3 guide
Standard cell libraries, IO libraries and memory compilers are designed, characterised at the agreed corners on the current models, checked by library QA and released with all their views.
Gate codes
In: PDK lifecycle
The first processed wafers are back and light couples into and out of the test structures and circuits, so measurement and correlation can start.
Gate codes
Writes the logic in a hardware description language or through high-level synthesis, integrates IP cores, and owns the pin assignment and timing constraints.
Discipline codes
In: FPGA lifecycle
A structured review of how a design or process can fail, what the effect would be and what prevents it.
Quality and reliability
Used in: FMEA guide, APQP lifecycle: Quality engineering (FMEA and control plan)
An FMEA that also counts how well safety mechanisms detect each failure, used to compute safety metrics.
Safety and security
Used in: Automotive lifecycle: Safety Analyses: FMEDA, FTA & DFA
A recurring engineering release: each further density, package or temperature grade is released with its own timing data, test program and qualification, by similarity to an earlier member where the evidence allows.
Gate codes
Owns the thesis, the company's direction and its biggest choices: what to build, what to build in-house and what to buy or partner for, when to raise money and from whom, and who to hire first.
Discipline codes
A chip whose logic can be configured after manufacture, used in products and to prototype other chips.
Design and verification
Used in: FPGA lifecycle, SoC lifecycle: FPGA prototyping, Soft IP lifecycle: IP FPGA prototyping, FPGA lifecycle: System & FPGA Architecture, FPGA lifecycle: FPGA logic design, FPGA lifecycle: FPGA verification, and 7 more
Maps the chip's RTL onto FPGA boards that run near real speed, giving software and silicon validation teams a platform before silicon.
Discipline codes
In: SoC lifecycle
The first customer order for production quantities is booked against the released part at the approved price, turning a design win into revenue and starting the delivery commitments the ramp must meet.
Gate codes
Runs synthesis, placement and routing with the FPGA vendor's tools, closes timing and builds the bitstream.
Discipline codes
In: FPGA lifecycle
The first parts from the new wafers are assembled in their package and run on the tester with the test program, so tested parts can go to bring-up and the test program has met real silicon.
Gate codes
In: SoC lifecycle
Handles customer returns and field failure analysis, runs the product change notification process, monitors safety-relevant field issues, and plans for obsolescence and end of supply.
Discipline codes
Analyses customer returns and field failures, leads problem solving with 8D or an equivalent method, feeds causes back into the FMEAs and control plans, and keeps the lessons learned database.
Discipline codes
In: APQP lifecycle
The end of software support is announced to customers with the date of the final release and the migration path.
Gate codes
The first production units have shipped against customer purchase orders under a supply agreement, and the company is invoicing for product rather than for evaluation or development work.
Gate codes
The project's experience is reviewed: accuracy seen on live work against the qualification baseline, overrides, errors found and escaped, effort saved and the review load it created.
Gate codes
The first flight lots are screened, pass lot acceptance and ship with their data packs, certificates of conformance and export authorisations.
Gate codes
In: Space lifecycle
A recurring review of field failures, returns, vulnerabilities, customer integration issues and modifications, deciding whether the safety and security case still holds and whether certificates need updating.
Gate codes
The density range, the hard IP set, the package options, the speed and temperature grades and the software support the family needs are written down and agreed by product, architecture and software leads.
Gate codes
The first wafers or packaged parts from the design release are back and pass their first power-up and basic tests, so bring-up and validation can start and the business can confirm or reset the sample dates it has given customers.
Gate codes
In: Product lifecycle, SoC lifecycle, AI accelerator lifecycle, Memory lifecycle, Space lifecycle, RF lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
Packaged test chips are back, power up and respond on the test boards, so measurement and reliability testing can start.
Gate codes
First wafers or packaged parts arrive and start testing, with the debug team, the tester time and the bench equipment ready.
Gate codes
Packaged product silicon has arrived and powers up on the evaluation board, and the bring-up team has started working through the silicon validation plan.
Gate codes
Gets tools installed and keeps them running: installation and site preparation procedures, start-up and acceptance tests, maintenance procedures and training, service delivery and escalation, spare parts planning and the register of every installed tool and its configuration.
Discipline codes
Plans and runs the functional safety lifecycle: roles, competence, independence, configuration and change control, the safety case, confirmation measures and the functional safety assessment.
Discipline codes
Supports customers once the system ships: service and repair, field issues and returns, field quality reporting, spares and the support commitments until the end of support.
Discipline codes
In: System lifecycle
The confirmation measures are complete, the functional safety assessment gives a positive judgement, and the safety case and safety manual are released.
Gate codes
Plans and manages the safety lifecycle under ISO 26262: the safety plan, the confirmation measures and their independence, the safety case and the safety culture of the project.
Discipline codes
Estimates utility demand, designs, installs and commissions the cleanroom air, ultrapure water, gas, chemical, cooling, vacuum, exhaust, abatement, waste treatment and power systems, readies tool hook-up and runs and improves the systems in operation.
Discipline codes
The first customer designs, on shuttles or full mask sets, are taped out on the node with certified tool flows and the IP they need.
Gate codes
A top-down analysis of the combinations of faults that can lead to a hazard.
Safety and security
Used in: Automotive lifecycle: Safety Analyses: FMEDA, FTA & DFA
The first process tools are moved into the cleanroom and set in their bays, with hook-up points, logistics and the integrated move-in schedule ready for the rest.
Gate codes
Tests the assembled unit through its die-to-die links, applies lane repair, and runs burn-in and system-level test, releasing the final test program with the package qualification.
Discipline codes
One live project is approved to use the step under an adoption plan, with its users briefed on the known limitations, enhanced review in place and the fallback flow ready.
Gate codes
The first device wafers are out of the fab on the frozen baseline, with wafer-level test data, and the characterisation plan and equipment are ready.
Gate codes
The first MEMS wafers and interface ASIC wafers are out, probed and ready to be built into prototype assemblies.
Gate codes
Writes the boot code, drivers and reference software that run on the chip.
Discipline codes
In: SoC lifecycle
Writes the firmware that runs on the chip's own controllers, such as power management, system control and security cores, often on a real-time operating system or bare metal, and the boot loaders that carry the chain of trust from the boot ROM to the operating system, and keeps them updated in the field.
Discipline codes
Designs the secure boot chain and writes the boot ROM security code, security firmware and cryptographic libraries, then writes the fixes that security updates deliver.
Discipline codes
Writes the boot code, firmware and board support the system runs on, first on the virtual prototype and the emulation and FPGA prototypes, then on the real boards, and keeps updating it in the field.
Discipline codes
In: System lifecycle
Writes the boot code, firmware and board support shared by the platform's products, first on the virtual platform and prototypes, then on the lead product's silicon, and maintains them for every derivative.
Discipline codes
Writes the on-chip or host firmware, drivers and algorithms: filtering, compensation from the calibration coefficients, sensor fusion where relevant and the configuration interface, and maintains them after release.
Discipline codes
The first full-flow wafers complete the process at the new fab and are measured, showing the flow runs end to end.
Gate codes
A compound semiconductor used for efficient power conversion and high-frequency RF parts.
Devices and interfaces
Used in: Power and compound lifecycle
The sponsor accepts the gap assessment as the starting point, with each gap ranked by its risk to the target profile.
Gate codes
The generation's densities, interface standard, target customers and bit cost goals are agreed, with a business case that justifies cell and array work.
Gate codes
In: Memory lifecycle
The graphics-optimized DRAM standard used in discrete GPUs and game consoles — wider and higher-clocked than system DDR but, unlike HBM, mounted conventionally on the board rather than stacked on an interposer, trading some bandwidth density for much lower cost and packaging complexity.
Standards and regulations
Used in: GDDR6 in the standards register
The EU regulation on processing personal data.
Export, trade and product lawStandards and regulations
A processor with many parallel cores, used for graphics and for AI training and inference.
Devices and interfaces
A growth round, from investors, strategic partners or debt suited to a revenue-stage company, is in place to pay for volume, sales, support and the next product.
Gate codes
The way the part will meet its radiation requirements is chosen and justified: by process, by design or both, on a technology whose radiation response and supply life are understood.
Gate codes
In: Space lifecycle
Defines what the macro does on the chosen process: its interfaces and pins, its operating corners, its area and power, and the views an integrator receives.
Discipline codes
Stacked memory dies placed next to a processor in the package for very wide, fast memory access.
Devices and interfaces
Used in: Memory lifecycle: Stacking, HBM & Packaging Integration
JEDEC's third-generation High Bandwidth Memory standard — 2.5D-stacked DRAM connected to a host die (GPU, AI accelerator) through a silicon interposer, trading raw clock speed for an extremely wide (1,024-bit per stack) bus.
Standards and regulations
JEDEC's fourth-generation High Bandwidth Memory standard, ratified with AMD, Google, Meta, Micron, Nvidia, Samsung, SK hynix and Synopsys as contributors.
Standards and regulations
Produces what an integrator builds with: the abstract, the timing and power views across corners, the behavioural and circuit models, and their correlation with silicon.
Discipline codes
Designs the digital logic with its mitigation in place, selects hardened cells and memories, and checks that synthesis and optimisation keep every redundant and protected element the mitigation needs.
Discipline codes
In: Space lifecycle
Implements the root of trust, fuse and key storage controllers, access control and isolation logic, and checks the provenance of security IP, following secure design rules and fixing what reviews and verification find.
Discipline codes
Designs the macro: design code for a digital macro, schematics and circuit simulation for an analog or mixed-signal one, through layout fixes to silicon debug and later ports.
Discipline codes
The architecture and RTL, with all safety mechanisms, are complete and frozen.
Gate codes
Builds the macro's test modes and built-in self-test, generates its test patterns, and writes the test chip test program and the production test patterns integrators reuse.
Discipline codes
The circuit or design code, the floorplan and the test approach are reviewed against the specification, and the choices that shape the layout are agreed.
Gate codes
Verifies the macro before and after layout: functions, corners and, for analog circuits, process variation, then correlates the models with silicon.
Discipline codes
Works with the foundry on the process, the kit and rule deck versions, the shared wafer run, the masks and the test chip wafers, and follows process changes after release.
Discipline codes
Every hard IP block has a source, a version and an integration specification, and its place in the device floorplan and its connection to the fabric, clocks and configuration logic are agreed.
Gate codes
Selects, licenses or designs the transceivers, memory interfaces, protocol controllers and processor subsystems built into the device, and integrates each with the fabric, the clocks and the configuration logic.
Discipline codes
Turns the design into layout on the target process: the floorplan, pins and power grid, placement and routing or custom layout, and the final layout database.
Discipline codes
Turning an algorithm written in a software language into hardware logic automatically.
Design and verification
Used in: FPGA lifecycle: RTL & HLS Design
The final layout is clean against the foundry's sign-off checks with the agreed kit version, verification after layout meets the specification at every corner, and the technology risks carried to silicon are recorded.
Gate codes
The macro is approved for development, with the target process, the SoC programmes or licensees that need it, and a target date for silicon proof.
Gate codes
Owns the macro's business case, its integrators and licensees, the process ports on the roadmap, the releases and the end of support.
Discipline codes
Runs the foundry's sign-off checks on the macro and on the test chip, with the agreed kit and rule deck version, and extracts the parasitics for verification and characterisation.
Discipline codes
Runs the quality checklist on the deliverables before silicon and with the silicon evidence, and builds the versioned release packages.
Discipline codes
The complete deliverable set, with the silicon and reliability evidence, has passed the quality checklist.
Gate codes
Probe cards, load boards, sockets and any burn-in or system-level test boards are built, inspected and checked out on the tester, so that silicon problems are not confused with hardware problems.
Gate codes
Sets the reliability requirements, reviews the layout for electrostatic discharge, latch-up and electromigration, and runs the reliability stresses on the test chip.
Discipline codes
The macro's specification, interfaces, pin list, operating corners and deliverable views are baselined with the integrating teams; later changes go through change control.
Gate codes
A protected hardware block or device that stores keys and performs cryptography.
Safety and security
Plans and builds the test chip that proves the macro: the measurement structures, interface and pads, the shared wafer run, the packages and the test boards.
Discipline codes
A reliability stress test that runs parts hot and powered for a long time to find early failures.
Quality and reliability
Owns the hardware validation and verification plans, requirements validation, the trace data, simulation and in-target tests, elemental analysis or other advanced methods for the most critical hardware, and the hardware verification results, with the independence the level requires.
Discipline codes
Plans and runs the measurements on the test chip that prove the macro against its specification, and publishes the silicon report and errata.
Discipline codes
Full production of a process or product, after risk production and ramp.
Manufacturing, test and packaging
The node is released for high-volume manufacturing with production recipes, a process control plan and the capacity plan in place.
Gate codes
Designs the boards, power supplies, isolation barriers, patient connections and enclosure electronics, places the means of patient and operator protection, and runs hardware bench tests before type testing.
Discipline codes
Owns the hardware design plan, the hardware requirements, the conceptual and detailed design of programmable devices, ASICs and boards, and the hardware build, following DO-254 at the assigned level.
Discipline codes
Designs the boards, power stages and isolation barriers to the safety concept and the insulation concept, with EMC-aware layout and components approved for the temperature, life and supply needed.
Discipline codes
Where hardware engineering is in scope, derives hardware requirements, designs the hardware and its interfaces to software, verifies the design and the built hardware against its requirements, and keeps it traceable to the system level.
Discipline codes
Specifies and verifies the hardware security functions the item relies on, such as a hardware security module, secure boot, key storage, cryptographic acceleration and debug protection, and provides chip-level evidence and a security manual to integrators.
Discipline codes
Writes the RTL with the safety mechanisms built in, such as lockstep cores, error correcting codes, parity, watchdogs and monitors, and fixes the bugs and safety gaps verification finds.
Discipline codes
Develops the modules that stack or bridge dies: interposer and bridge fabrication, through-silicon vias, temporary bonding, thinning and debonding, micro-bumps, and die-to-wafer or wafer-to-wafer hybrid bonding with its surface preparation and alignment.
Discipline codes
Every customer and supplier relationship that shares cybersecurity work has an agreed interface agreement saying who does what, which work products are exchanged, and how vulnerabilities and incidents are reported.
Gate codes
Plans and runs the audit programme with qualified auditors: system audits against the standards, process audits, product audits and the follow-up of findings, and checks that layered process audits are effective.
Discipline codes
In: QMS lifecycle
Defines what the block does, its interfaces and the configuration options an integrator can choose, and supports the specification until the block is verified.
Discipline codes
The group of vehicle makers and associations behind the IATF 16949 quality standard.
Standards bodies and agencies
Used in: IATF 16949 guide, Interoperability and compliance overlay, Traceability overlay
The automotive quality management standard of the International Automotive Task Force.
Standards and regulations
Used in: IATF 16949 guide, Interoperability and compliance overlay, Traceability overlay
A model format that describes how a chip's pins behave electrically, for board signal integrity work.
Design and verificationStandards and regulations
A periodic review of how the installed tools perform for customers: uptime, field reliability, spares, service cost and customer satisfaction, and what the platform needs next.
Gate codes
Leadership agrees that a new fab or fab phase is worth studying and funds a team to build the business case.
Gate codes
Management reviews whether the improvement actions worked, the lessons are in the standard process set, and any follow-up assessment is planned or complete.
Gate codes
A company's written programme of controls for meeting export rules.
Export, trade and product law
Used in: Export control overlay
Adds the block's own test structures and patterns so the SoC team can connect them into the chip's test plan.
Discipline codes
A chip company that designs and also manufactures its own chips.
Business and product lifecycle
Proves the block meets its specification in each supported configuration, and often supplies verification IP the SoC team reuses.
Discipline codes
Every process has run long enough to produce records that show it works: training, calibration, supplier control, control plans, nonconformance handling and measures reported.
Gate codes
In: QMS lifecycle
The international body for electrical and electronic standards, such as IEC 61508.
Standards bodies and agencies
Used in: Standards and compliance guides, Medical lifecycle: Device Software Development to IEC 62304, Medical lifecycle: Device software (IEC 62304), IEC 62304 guide, IEC 60601 guide, IEC 62366-1 guide, and 15 more
The family of standards for the safety of medical electrical equipment and systems.
Standards and regulations
Used in: IEC 60601 guide
The generic functional safety standard for systems built from electrical, electronic and programmable electronic parts that carry out safety functions.
Standards and regulations
Used in: IEC 61508 guide, Functional safety overlay, Traceability overlay, AI governance overlay
The process industry's functional safety standard, derived from IEC 61508, for the safety instrumented systems that protect plants such as refineries, chemical works, power stations and pipelines: sensors, logic solvers and final elements that bring a process to a safe state when it goes out of control.
Standards and regulations
Used in: IEC 61511 guide
The international series for communication in substations and, increasingly, across power utility automation, including distributed energy resources and hydro plants.
Standards and regulations
Used in: IEC 61850 guide
The lifecycle processes for software that is a medical device or part of one: development, maintenance, software risk management, configuration management and problem resolution, with the documentation and testing depth scaled by a software safety class.
Standards and regulations
Used in: IEC 62304 guide, Functional safety overlay, Traceability overlay, AI governance overlay, Medical lifecycle: Device Software Development to IEC 62304, Medical lifecycle: Device software (IEC 62304)
The usability engineering process for medical devices: understand the users, uses and environments, find the user interface characteristics and use scenarios that could lead to harm, design and evaluate the user interface, and show through a summative evaluation that hazard-related use is safe.
Standards and regulations
Used in: IEC 62366-1 guide
The hazard-based safety standard for audio, video, information and communication technology equipment.
Standards and regulations
The international standard for obsolescence management: policy, planning, proactive and reactive strategies and their review.
Standards and regulations
Used in: Obsolescence management overlay
A series of standards for the security of industrial automation and control systems, written for the asset owners who run them, the integrators and service providers who build and maintain them, and the product suppliers whose components go into them.
Standards and regulations
Used in: IEC 62443 guide, Security overlay, Traceability overlay
The IEC standard and declarable substance list for material declarations in the electrotechnical industry.
Standards and regulations
The security lifecycle standard for health software, including software in medical devices.
Standards and regulations
Used in: IEC 81001-5-1 guide
The international scheme for certifying equipment used in explosive atmospheres.
Export, trade and product law
Used in: ATEX and IECEx guide
The boundary-scan test access port standard, known as JTAG, used for board test and device access.
Standards and regulations
The embedded core test standard, with a wrapper that gives standard test access to cores inside a chip.
Standards and regulations
A standard for access to embedded instruments inside a device through a test access port, known as IJTAG.
Standards and regulations
For a large or software-heavy block, runs the block's RTL on an emulator, on its own or in a small harness system, so long tests, many configurations, the reference driver and performance workloads run before release.
Discipline codes
Where a block is prototyped on its own, maps it onto an FPGA to test it at speed with real interfaces and software, and demonstrates it to licensees.
Discipline codes
A power switch for high voltages and currents, used in motor drives and inverters.
Devices and interfaces
Every IP block in the SoC is selected, received from its IP lifecycle or supplier, and connected, so full-chip RTL work can close.
Gate codes
In: SoC lifecycle
Produces what an integrator needs to implement a soft block: the timing constraints, a reference synthesis on a target process and the timing models, and, where offered, the abstract views of a reference hardening.
Discipline codes
Management accepts the reason for the program, names a sponsor and funds the scoping work.
Gate codes
Keeps the catalogue of what the platform can reuse, sources and licenses third-party IP, checks each derivative's licence position and archives the IP when the platform retires.
Discipline codes
Synthesises each customer design to the configurable cells, places and routes it on the fixed base, closes timing within the custom layers and tapes out the custom layers.
Discipline codes
The block's internal structure, interfaces to the integrator, register map and configuration logic are reviewed against the specification, and the verification plan is agreed, before RTL coding builds on them.
Gate codes
Prepares and runs incident response: the plan and its rehearsals, triage, containment, root cause analysis with suppliers, remediation, communication with customers, authorities and partners, and lessons learned.
Discipline codes
Plans and runs the prototype builds, brings boards, chips, firmware and software up together in the lab, and keeps the integration issue list until the design is frozen.
Discipline codes
In: System lifecycle
Chooses each IP block, takes its release from the IP lifecycle or a supplier, and connects it into the SoC.
Discipline codes
In: SoC lifecycle
Writes the technology definition, joins the modules into one flow, tunes the devices, freezes the baseline and owns the integrated process through qualification.
Discipline codes
Builds and owns the fab business case: demand, capital, financing, wafer cost and return, the final investment decision, and the later reviews that decide whether to expand, convert or exit.
Discipline codes
Designs the interface to the JEDEC standard the product follows: the I/O, data path, clocking and training features of DDR, LPDDR, GDDR or HBM, the NAND interface, and for HBM the base die and its connection through the stack.
Discipline codes
In: Memory lifecycle
A reusable, licensable design block, such as a processor core or an interface, that is integrated into a chip.
Design and verification
Used in: Soft IP lifecycle, SoC lifecycle: IP Integration, SoC lifecycle: IP integration complete gate, SoC lifecycle: IP integration, Soft IP lifecycle: IP Specification & Architecture, Soft IP lifecycle: IP Verification, and 48 more
The repaired or new standard processes are reviewed, and the improvement plan with its owners, resources and timetable is approved.
Gate codes
Decides which blocks to license rather than design for the test chip, evaluates and negotiates for them, integrates them and supports them on test chip silicon.
Discipline codes
Designs and verifies the platform's IP blocks and subsystems to a reuse standard, configures them for each derivative and keeps them maintained for every product that uses them.
Discipline codes
An XML format for describing IP blocks, their registers, interfaces and configuration, so tools and teams can exchange them without manual re-entry.
Standards and regulations
The block is approved for development or licensing, with the SoC programs that need it and a target date.
Gate codes
The electronics assembly association that publishes board, assembly and materials declaration standards.
Standards bodies and agencies
The IPC standard for materials declarations, giving a common data format for declaring the substances in a part.
Standards and regulations
For performance-critical blocks, sets throughput, latency and power targets, tracks them on every RTL drop and checks the frozen design against them.
Discipline codes
Owns the block's roadmap, the SoC teams and customers that use it, and its releases and support.
Discipline codes
The platform's IP blocks and subsystems are verified for every supported configuration and meet the reuse standard: documented, configurable, with known limits and licence terms recorded.
Gate codes
Plans the quality checklist, collects the evidence as the block matures, runs the checklist on the complete deliverable set and builds the versioned release package.
Discipline codes
The complete deliverable set has passed the quality checklist, whether it was built in-house or received from a supplier.
Gate codes
A versioned release package goes to the SoC teams, with its documentation and a route for support.
Gate codes
Each incident is closed with its cause understood, remediation delivered and lessons applied to the item, the process and the next projects.
Gate codes
Runs the product security incident response team: the public reporting channel, triage and severity rating, coordination of fixes, coordinated disclosure, CVE identifiers and security advisories until the end of support.
Discipline codes
Works out the block's micro-architecture and writes its design code and the configuration and interface logic an integrator connects to.
Discipline codes
The block's specification, interfaces and configuration options are baselined; later changes go through change control.
Gate codes
The international body that publishes standards such as ISO 9001 and ISO 26262.
Standards bodies and agencies
Used in: Standards and compliance guides, ISO 9001 guide, ISO 26262 guide, ISO 26262-11 guide, ISO 21448 guide, ISO/SAE 21434 guide, and 15 more
The most widely used quality management standard.
Standards and regulations
Used in: ISO 9001 guide, Interoperability and compliance overlay, Traceability overlay, AI governance overlay
A CAN-based communications standard between tractors and the implements towed behind them — lets a plow, planter or sprayer from one manufacturer talk to a tractor's cab display and control system from another, the interoperability layer underneath modern precision agriculture.
Standards and regulations
The quality management system standard for organisations that design, make, install or service medical devices, or supply parts and services to those that do.
Standards and regulations
Used in: ISO 13485 guide
The machinery standard for designing and validating the parts of a machine's control system that carry out safety functions, such as stopping on a guard opening, limiting speed or preventing unexpected start-up.
Standards and regulations
Used in: ISO 13849 guide
The international standard for an environmental management system: how an organisation understands its environmental aspects, meets its compliance obligations and improves its environmental performance, usually confirmed by an accredited certification body.
Standards and regulations
Used in: ISO 14001 guide
The risk management process for medical devices across their whole life: plan, analyse, evaluate, control, judge the overall residual risk against benefit, review, and keep learning from production and post-production information.
Standards and regulations
Used in: ISO 14971 guide
The standard for the safety of the intended functionality, known as SOTIF: avoiding unreasonable risk from hazards caused by functional insufficiencies of the intended function, such as performance limits of sensors and perception, or by reasonably foreseeable misuse, when nothing has failed.
Standards and regulations
Used in: ISO 21448 guide
The ISO standard for engineering software updates for road vehicles at the organisation, project, infrastructure, vehicle and control unit levels.
Standards and regulations
Used in: ISO 24089 guide
The international standard for functional safety of electrical and electronic systems in series production road vehicles.
Standards and regulations
Used in: ISO 26262 guide, Functional safety overlay, Traceability overlay, AI governance overlay, ISO 26262-11 guide
A deep dive into ISO 26262-11, the guidance part of ISO 26262 for semiconductors, for IP, SoC, microcontroller, memory, analog, power management and sensor suppliers.
Standards and regulations
Used in: ISO 26262-11 guide
The international standard for an occupational health and safety management system: how an organisation prevents work related injury and ill health by identifying hazards, involving workers and controlling risks, with certification by accredited bodies.
Standards and regulations
Used in: ISO 45001 guide
Guidance on managing the risks that AI brings to an organisation, built on general risk management practice.
Standards and regulations
Used in: AI governance overlay
The international standard for an information security management system: how an organisation assesses information security risks, selects controls from a reference set or elsewhere, records them in a Statement of Applicability, and improves, with certification by accredited bodies.
Standards and regulations
Used in: ISO/IEC 27001 guide, AI governance overlay
The international standard for an artificial intelligence management system: how an organisation that develops, provides or uses AI systems governs them responsibly, assesses AI risks and impacts on people, and applies controls, using the same management system structure as ISO 9001 and ISO/IEC 27001.
Standards and regulations
Used in: ISO/IEC 42001 guide, AI governance overlay
A publicly available specification that gives guidance for auditing an organisation's cybersecurity management for road vehicles, building on the general audit guidance of ISO 19011 and the organisational expectations of ISO/SAE 21434.
Standards and regulations
Used in: ISO/PAS 5112 guide
The joint ISO and SAE standard for cybersecurity engineering of road vehicle electrical and electronic systems, from concept through development, production, operation and maintenance to decommissioning.
Standards and regulations
Used in: ISO/SAE 21434 guide, Security overlay, Traceability overlay, AI governance overlay
Builds a transaction-level model of the block, for example in SystemC, so SoC teams can put it in their virtual platform before its RTL exists, and keeps it in step with the RTL to the release.
Discipline codes
The computers, networks and business systems of an organisation.
Devices and interfaces
Used in: AI-assisted flow lifecycle: IT security and infrastructure, IEC 81001-5-1 guide
Builds and tests complete tools: integration and test plans, the prototype build, evaluation tool builds, test procedures, and the factory acceptance test that every production tool must pass before it ships.
Discipline codes
The US rules for defence articles, defence services and related technical data.
Export, trade and product law
Used in: ITAR and EAR guide, Export control overlay
Evaluates blocks from suppliers, agrees the licence, checks each delivery from the supplier and accepts the final one before it goes to SoC teams.
Discipline codes
The intended use, indications, users and use environments are written down and approved, the device is classified for each target market with a recorded rationale, and the regulatory strategy names the route to market and the evidence it needs.
Gate codes
Integration verification, software verification and system verification are complete for the release, with results traced to requirements and a release note issued.
Gate codes
Security functions are implemented and integrated, and verification shows each cybersecurity requirement is met with no open weakness above the agreed level.
Gate codes
The test structures, timing constraints, reference synthesis and timing models are ready for an integrator.
Gate codes
Coverage goals in the IP verification plan are met in every supported configuration, and every open bug is fixed or waived.
Gate codes
One or more lead customers commit to developing the technology with the packaging provider, with shared requirements, responsibilities, information rules and the path from feasibility to volume agreed in writing.
Gate codes
The industry body that sets memory, packaging and reliability standards for semiconductors.
Standards bodies and agencies
Used in: Memory lifecycle: Component Qualification (JEDEC), Obsolescence management overlay, Interoperability and compliance overlay
The JEDEC standard for customer notification of product and process changes by semiconductor suppliers.
Standards and regulations
Used in: Obsolescence management overlay
The JEDEC standard for product discontinuance: how suppliers notify customers that a product will be discontinued and offer a final order window.
Standards and regulations
Used in: Obsolescence management overlay
The common name for the test access port and boundary scan standard used for board test and chip debug.
Design and verification
Every released version, its tool versions and its QA results are archived so existing designs can still be checked and reproduced after support ends.
Gate codes
In: PDK lifecycle
A bare die tested well enough to be trusted before it is assembled with others in a package.
Manufacturing, test and packaging
The wafer sort program for each die meets the agreed known-good-die quality, and a bank of tested dies is ready for assembly.
Gate codes
Wafer-level optical and electrical measurements are correlated with the models, and the criteria that decide which dies go on to assembly are agreed and released.
Gate codes
Sets the test strategy that brings each die to known-good-die quality at wafer sort, develops the sort program and probe hardware, runs it, and manages the bank of tested dies.
Discipline codes
The whole kit passes its QA test cases and QA designs in every supported tool category, the parts of the kit agree with each other, and the reference flows are certified.
Gate codes
In: PDK lifecycle
Known good die testing, stack assembly and stack test are proven, and stacked or packaged samples meet their targets, so stacks can be offered to system makers and package integrators.
Gate codes
In: Memory lifecycle
Sets the laser requirements, chooses and qualifies how the laser is integrated, and secures laser supply for production.
Discipline codes
Draws the photonic layout, places the fibre interface, runs design rule, connectivity and post-layout checks that understand curved waveguides, and prepares the tape-out database.
Discipline codes
Draws the RF layout with symmetric, well-grounded and isolated structures, runs physical verification and reliability checks, and assembles the database for tape-out.
Discipline codes
In: RF lifecycle
The link budget closes on paper with margin: laser power, every coupling and component loss, receiver sensitivity and the allowance for ageing and temperature add up for the target reach and data rate.
Gate codes
The final builds are complete, remaining materials are used or disposed of, tools are redeployed and the process, quality and reliability records are archived.
Gate codes
Designs and checks out load boards and selects sockets and handler change kits for final test, with signal and power integrity analysis, and maintains them and their spares in production.
Discipline codes
The custom layout is drawn and passes design rule and layout versus schematic checks.
Gate codes
In: AMS lifecycle
Top management decides to establish or renew a certified quality management system, names the people accountable for it and commits the resources to start.
Gate codes
In: QMS lifecycle
A periodic review of the mature product: revenue and margin, quality, supply risks and successors are weighed, and the product is kept, refreshed or moved towards phase-down.
Gate codes
Lead customers' product designs pass the joint design review and their first sample builds start on the pilot line, with known limits stated.
Gate codes
Forms the company and protects what it owns: founder and employee agreements, IP assignment, patents, confidentiality, the foundry, EDA, IP and design partner agreements, export classification and the first customer supply agreement.
Discipline codes
Agrees the evaluation terms, reviews licence, confidentiality, training rights and output ownership for production use, assesses export control, writes disclosure guidance and reviews every change of terms.
Discipline codes
Production test limits and guard bands are set from characterisation data across corners, voltage and temperature, so the parts that pass meet the datasheet with the agreed margin.
Gate codes
Negotiates the licences and partner agreements the product depends on, reviews intellectual property risk, classifies the product for export control, makes the product compliance declarations, and reviews customer notices and terms.
Discipline codes
Writes the optimised kernels and the collective communication library, integrates the stack with the machine learning frameworks developers use, and assembles, tests and publishes each software release.
Discipline codes
Designs and characterises the configurable cells, writes the custom layer rules and the reference flow, releases the design kit, correlates it with silicon and keeps it updated.
Discipline codes
Chooses and develops the patterning approach for each layer, builds the optical proximity correction models, and prepares the mask sets for test vehicles.
Discipline codes
Designs packing, labelling and traceability marking to the customer's standards, evaluates packaging in the trial, and confirms capacity and delivery against the customer's demand.
Discipline codes
In: APQP lifecycle
The low-power memory interface family used in phones, laptops and cars.
Devices and interfaces
A speed-graded extension of JEDEC's low-power DDR5 mobile-memory standard, pushing per-pin data rates higher for flagship phones and, increasingly, power-constrained edge-AI inference chips that need HBM-class bandwidth without HBM's packaging cost.
Standards and regulations
Used in: LPDDR5X in the standards register
JEDEC's newest mobile/low-power memory generation, ratified alongside the broader DDR6-era refresh of the standard's signaling and channel architecture — built for the combination of on-device AI inference and battery-life pressure in next-generation phones and edge devices.
Standards and regulations
Used in: LPDDR6 in the standards register
The product is on the market: prices and ordering information are published, sales and channel partners are trained, launch content is out and support processes are running.
Gate codes
The product's cost, yield, quality, demand and competitive position are reviewed, and the next generation, further cost-downs or a discontinuance are decided.
Gate codes
In: Power and compound lifecycle, MEMS and sensors lifecycle, System lifecycle
The go or no-go for the market announcement: launch materials, channel stock, sales and partner training, support and the compliance declarations are checked ready, and the announcement date is confirmed.
Gate codes
With the laser source chosen at the architecture freeze, the laser supply is agreed and the laser attach and integration design is released, with its optical power, efficiency, thermal and reliability assumptions written into the link budget and the package design.
Gate codes
The final orders are built, calibrated, tested and shipped, and the design, process, calibration and test records are archived.
Gate codes
The photonic layout passes its design rule and connectivity checks, post-layout simulation still meets the targets, and the electronic die and package interfaces match it.
Gate codes
The final chance for customers to order a discontinued product before supply stops.
Business and product lifecycleGate codes
In: Obsolescence overlay, Product lifecycle, SoC lifecycle, FPGA lifecycle, Automotive lifecycle, Space lifecycle, Photonics lifecycle, Power and compound lifecycle, RF lifecycle, Industrial lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
The lead product, built from the platform, is validated on silicon and hardware, and the platform technology it proved is confirmed ready to be frozen as a baseline for reuse.
Gate codes
A check that the layout implements the same circuit as the schematic or netlist.
Design and verification
The final wafers covering confirmed last orders are started, equipment and materials are planned to the end, and the process record is archived.
Gate codes
The authority or notified body has cleared, approved or certified the device for the target market, the declaration of conformity is signed where it applies, and registrations are made, so the device may be placed on that market.
Gate codes
Management decides to set up the organisation's cybersecurity management system, or to extend it to new products, sites or markets, names an accountable executive and gives the owner of the system the time, budget and authority to build it, before any process is written or any project relies on it.
Gate codes
Decides how the system is split into dies, the node of each die, the packaging technology and the power and thermal budget of the whole package, and signs off system power and thermal at the multi-die sign-off.
Discipline codes
Each unit process meets its own capability targets on the chosen tools and materials, so the modules can be joined into one flow.
Gate codes
Prototype measurements agree with the multiphysics and system models closely enough that the models can be used to set calibration, package and test decisions, with any redesign identified.
Gate codes
Keeps measuring and test equipment fit for purpose: calibration to traceable references, the laboratory scope, measurement system analysis for the gauges and testers in the control plans, and the reaction when equipment is found out of calibration.
Discipline codes
In: QMS lifecycle
The case for building the product from several dies, rather than one large chip, is accepted and a team is funded.
Gate codes
Before the device design is frozen, the team shows that the substrate and epitaxy material and the device concept can meet the blocking voltage, on-resistance and robustness targets, from simulation, test structures and material data.
Gate codes
The module substrate, the transitions between die, package and board, and the antenna design are frozen for the module build, with electromagnetic models that include the package.
Gate codes
In: RF lifecycle
The EU regulation that medical devices must meet before they are placed on the market.
Export, trade and product law
Used in: EU MDR guide, Medical lifecycle
Assembly-level checks pass across dies, interposer and substrate on the exact versions to be released, and cross-die verification is closed on the frozen dies.
Gate codes
Verifies the system across die boundaries, through simulation and emulation of the dies together with their die-to-die links, building its environment alongside the dies and signing off at the multi-die sign-off.
Discipline codes
Designs the enclosure, cooling and mechanical parts, from the thermal and mechanical concept through prototype parts to production tooling and environmental testing.
Discipline codes
In: System lifecycle
Tiny mechanical structures made with chip processes, such as accelerometers, microphones and pressure sensors.
Devices and interfaces
Used in: MEMS lifecycle, MEMS and sensors lifecycle: MEMS Process Development, MEMS and sensors lifecycle: MEMS process baseline freeze gate, MEMS and sensors lifecycle: First MEMS and ASIC wafers gate, MEMS and sensors lifecycle: MEMS transducer design, MEMS and sensors lifecycle: MEMS process development and integration
The software that tracks and controls each lot and tool step in a factory.
Manufacturing, test and packaging
Used in: Fab build lifecycle: Factory automation, MES and OT security
The compact models are fitted to measurements from the frozen process baseline, with the remaining gaps to target stated, so the next kit can support real design work.
Gate codes
In: PDK lifecycle
Qualifies suppliers and critical components, including the foundry and assembly partners for custom chips, builds pilot units, writes production test specifications, validates processes and releases production with unique device identification and traceability.
Discipline codes
Scales production, improves yield and keeps the supply running.
Discipline codes
In: SoC lifecycle
Introduces the product to manufacturing, programs and tests each unit, and manages component supply, including the FPGA device's own end-of-life notices.
Discipline codes
In: FPGA lifecycle
Models the cost of ownership, plans capacity, readies the fab for risk and volume production, transfers the process to further fabs where needed, and runs the final wafer starts.
Discipline codes
Plans and runs wafer starts, test and assembly capacity, die bank and inventory across grades, the ramp and the final builds, and delivers committed allocations.
Discipline codes
In: Memory lifecycle
Prepares and runs the fab as a factory: operations readiness, shift structure, wafer start and dispatch plans, maintenance, spares, cycle time and output, the factory performance report and continuous improvement, and the wind-down and customer transfers at the end.
Discipline codes
Plans the MEMS fab, ASIC foundry, assembly and test supply chain, orders prototype and production wafers, ramps capacity with calibration equipment included, tracks unit cost and runs the last-time-buy builds.
Discipline codes
Runs the pilot line and then volume manufacturing: lot starts, work instructions, inline inspection and process control, yield learning and defect reduction, cycle time, and the final builds at end of life.
Discipline codes
Assesses the process and package technology, places the mask and wafer orders, builds the first packaged parts, and plans capacity and long-term supply through to the last builds.
Discipline codes
Agrees wafer banking with the foundry, plans the bank, and builds, accepts and holds the base wafers that every customer design is finished on.
Discipline codes
The performance specification under which integrated circuit manufacturers have their design, wafer fabrication, assembly and test flows qualified and listed on the qualified manufacturers list for military and space use.
Standards and regulations
Used in: MIL-PRF-38535 guide, Interoperability and compliance overlay
A dual-redundant serial data bus that has carried avionics and weapons-system data on military and aerospace platforms since the 1970s — deliberately conservative and extremely well-proven, which is exactly why it's still specified on new defense programs despite far faster commercial alternatives existing.
Standards and regulations
Interface specifications for cameras, displays and sensors in phones and connected devices.
Devices and interfaces
MIPI Alliance's long-reach automotive SerDes physical layer — unlike MIPI CSI-2/DSI, which connect a sensor or display to a processor within centimeters, A-PHY carries data up to 15 meters across a vehicle at an extremely low target packet error rate, purpose-built for camera, radar and display links in ADAS and infotainment architectures.
Standards and regulations
Used in: MIPI A-PHY in the standards register
The branch of AI in which models learn patterns from data rather than following written rules.
Devices and interfaces
Sets up the pilot environment and data preparation, documents the model and its data in a model and data card, and builds and runs the drift monitoring once the step is in use.
Discipline codes
Collects cybersecurity information from the field and from suppliers, researchers and public sources, evaluates events, analyses and manages vulnerabilities, reports monitoring results and announces the end of cybersecurity support.
Discipline codes
Develops and sustains the unit processes, such as etch, deposition, implant, thermal steps, planarisation and cleans, to their capability targets on the chosen tools.
Discipline codes
Builds and releases the SPICE compact models: target models first, then models fitted to baseline silicon, process corners, statistical and mismatch models, and final models correlated to production silicon.
Discipline codes
In: PDK lifecycle
Builds the models customers and internal teams simulate with: compact SPICE models of the device including temperature and body diode behaviour, thermal network models of packages and modules, and the loss data behind online calculators, fitted to silicon and released with stated limits.
Discipline codes
Designs the module or antenna-in-package: substrate, filters and passives, die-to-package-to-board transitions, antennas and arrays, thermal paths, and builds and measures the module samples.
Discipline codes
In: RF lifecycle
The basic transistor of most chips, and a common discrete power switch.
Devices and interfaces
Owns the generation roadmap, the business case and bit cost targets, pricing, export classification, the product family and its mix, customer commitments and the decisions to shrink, add derivatives or withdraw a product.
Discipline codes
In: Memory lifecycle
Builds the coupled mechanical, electrostatic, piezoelectric, thermal, fluidic and acoustic models of the transducer and package, reduces them to behavioural models for circuit co-simulation, and correlates them with measured parts.
Discipline codes
A shared wafer run where several designs split the mask and wafer cost, often used for prototypes.
Manufacturing, test and packaging
Used in: MPW calendar, Photonics lifecycle: Photonic MPW & Tape-out
The package or power module, with its die attach, interconnect and substrate, has passed its own qualification, such as power cycling and thermal cycling, and its assembly process is frozen.
Gate codes
Plans manufacturing test of die, memory stacks and package, runs reliability qualification of the chip and the system, releases production and system-level test, and keeps quality and supply in control through to the final build.
Discipline codes
Builds the prototypes and type test samples, releases the production test program with the routine safety tests, owns the production control plan and traceability, and hosts factory inspections.
Discipline codes
The market requirements are reviewed with lead customers and approved, then baselined, so the business case and the product requirements that follow are judged against one agreed view of the market.
Gate codes
Errata fixes, view updates after foundry process changes and integration fixes are released as a new version, with notes that say what changed.
Gate codes
A recurring decision: each software release after launch is checked for correctness, performance and compatibility before it ships to customers.
Gate codes
At each agreed interval the reference reruns, drift indicators, override and error logs, incidents and corrective actions are reviewed, and the step is continued, restricted, requalified or put forward for retirement.
Gate codes
Cybersecurity monitoring, event evaluation, vulnerability management and incident response are staffed and running for the item in the field.
Gate codes
Top management has reviewed the system with all required inputs and recorded decisions on improvement, changes and resources, including readiness for the certification audit.
Gate codes
In: QMS lifecycle
A maintenance release of the platform's IP, firmware, software and tools is validated on the supported derivatives and released with its notes and advisories.
Gate codes
Assembled modules are measured as the customer will use them, including antenna patterns and beam steering for arrays, and are ready for pre-compliance testing and customer evaluation.
Gate codes
In: RF lifecycle
The substrate or interposer technology and the key materials are chosen with measured properties, supplier commitments for development quantities and a first view of volume supply.
Gate codes
Prepares and runs the building of tools: make or buy, should-cost, critical suppliers and their qualification, the released bill of materials, build instructions, supply plans, build quality and cycle time, standard cost and last-time buys of parts.
Discipline codes
Makes sure every gauge, metrology tool and tester that checks a characteristic in the control plan is capable: calibration, gauge studies, tester to tester correlation and guard band setting.
Discipline codes
In: APQP lifecycle
Prepares the system for volume: design for manufacture, suppliers and the approved vendor list, the validation and production builds, production test, the production bill of materials, the ramp and last-time buys.
Discipline codes
In: System lifecycle
Checking that a measurement or test is repeatable and accurate enough to trust its results.
Quality and reliability
Used in: MSA and SPC guide, APQP lifecycle: Metrology, test correlation and MSA, QMS lifecycle: Measurement, calibration and MSA
Turns system makers' needs and the JEDEC standards process into the product target specification: densities, interface generation, speed, power and capacity points, stack configurations for HBM, and the features the controllers on the other side need.
Discipline codes
In: Memory lifecycle
Selects and develops the substrate or interposer technology, dielectrics, underfills, mould compounds, thermal interface materials, solders and bonding layers with their suppliers, measures their properties and qualifies them.
Discipline codes
Builds the production trial and series parts: test programs and hardware released for production, operator training, the run at rate, and day to day control under the control plan, including part average testing where the customer requires it.
Discipline codes
In: APQP lifecycle
The matching set of die databases and interposer and substrate data, as signed off, is released to the foundries and suppliers and locked under change control.
Gate codes
Designs the physical tool: the platform and frame, process chambers, vacuum and gas delivery, fluid and thermal systems, wafer handling and robotics, and the drawings and models that manufacturing builds from.
Discipline codes
Non-volatile memory that keeps data without power, used in storage; named after the logic gate its cells resemble.
Devices and interfaces
NEBS is the long established set of physical, environmental, electromagnetic and electrical safety requirements that North American operators apply to equipment installed in their central offices and network sites.
Standards and regulations
Used in: NEBS guide
Designs the links between accelerators and between servers, the topology of racks and clusters, and the plan for collective communication, and proves them on hardware.
Discipline codes
The customer design is complete and synthesised to the configurable cells.
Gate codes
The US standards institute that publishes security, cryptography and AI risk guidance.
Standards bodies and agencies
Used in: Security overlay, AI governance overlay
The work of taking a new product from development into production.
Business and product lifecycle
A processor block designed to run neural network workloads efficiently.
Devices and interfaces
One-time costs of developing a chip, such as design, masks and qualification, as opposed to per-unit cost.
Business and product lifecycle
Used in: Business case tool
After a lifecycle review decides to phase the product down, it is marked not recommended for new designs: existing customers stay supplied, new design-ins are steered to a successor, and the status is shown on the datasheet and the product pages.
Gate codes
The O-RAN ALLIANCE defines open interfaces between the parts of a radio access network so that radio units, distributed units, central units and control software from different suppliers can work together.
Standards and regulations
Used in: O-RAN guide
The opportunity is judged worth a concept study: the customer need is real, it fits the strategy, and a small team is given time to shape a concept.
Gate codes
The assets, the security objectives, the assurance level aimed for and the secure development lifecycle the project follows are agreed and written into the security plan.
Gate codes
The Open Compute Project is a community that publishes open hardware specifications for data centre servers, storage, networking, racks, power, cooling, management and security.
Standards and regulations
Used in: OCP guide
A discontinuance notice or supply risk on a chip or component, or the end of the product's commercial life, is assessed, and a last-time buy, a redesign with its own change assessment, or the device's end of support is decided.
Gate codes
The company that designs and sells the end product, such as a vehicle or a phone.
Business and product lifecycle
Adjusting mask shapes so the printed pattern on the wafer matches the intended layout.
Manufacturing, test and packaging
Selects the ATE platform and test sites, transfers the program to production testers at the internal floor or a test subcontractor, proves capability, and runs the test floor through the ramp and end of life.
Discipline codes
Chooses the foundry and process for the test chip, books the shuttle, delivers the database for the run and tracks the test chips back to the lab with their cost and schedule actuals.
Discipline codes
Plans wafer, substrate, filter, assembly and test supply, readies the ramp, runs change notification with customers, and manages the last-time buy and the archive.
Discipline codes
In: RF lifecycle
Plans and builds optical test, from wafer probing through couplers to final module test: setups, test structures, measurements, known good die criteria, production test and yield data.
Discipline codes
A regular review of the supply chain, the technology, the package and the materials shows whether the part can still be supplied, and whether a die bank, a redesign or a last-time buy is needed.
Gate codes
In: Space lifecycle
A periodic review of the running fab: output, cost, yield, availability, safety, sustainability, workforce and incentive compliance, and whether capacity should change.
Gate codes
For tools that depend on light, plasma, electron beams or precise sensing: optical design, light and plasma sources, detectors, in-situ sensors and endpoint detection, calibration methods and tool-to-tool matching, as used in lithography, inspection and metrology tools and in the chambers of deposition and etch tools.
Discipline codes
A company that packages and tests chips for others.
Manufacturing, test and packaging
Selects and manages the outsourced assembly and test suppliers and the supply of wafers and substrates, gets their lines ready and plans their capacity.
Discipline codes
The control systems that run equipment and processes, such as the automation of a fab.
Devices and interfaces
Used in: Fab build lifecycle: Factory automation, MES and OT security
Updating a device's software through its wireless connection, common in vehicles.
Devices and interfaces
Product requirements, cost and price targets, schedule, make, buy or partner choices and resources are agreed, and the business commits the funding for full development.
Gate codes
A future node is put on the technology roadmap and a pathfinding team is funded to explore how it could be built.
Gate codes
The conditions for a bounded pilot are in place: what data may be used and where it may go, an evaluation agreement with the supplier, and the budget, people and isolated environment the pilot needs.
Gate codes
The integrated prototype passes its internal acceptance tests in the demonstration lab: functions, process results on test wafers, safety and early reliability.
Gate codes
Production is approved by the authority or accepted by the integrator, the obsolescence management plan is active and delivery of conforming units has started.
Gate codes
The customer has nominated the part or the business has approved a new automotive part, and a cross-functional APQP team is named with a leader, a schedule tied to the customer's program milestones and a list of the customer specific requirements that apply.
Gate codes
In: APQP lifecycle
Cost, schedule, resources and feature set are agreed between the business and engineering, and development of the system is committed.
Gate codes
In: System lifecycle
Owns the product assurance plan, the compliance evidence against QML or ECSS requirements, the parts, materials and processes list, the quality level and procurement specification, design reviews, nonconformance and the material review board, and the release of every flight lot.
Discipline codes
In: Space lifecycle
Develops and proves the process results the tool exists to deliver: process requirements with customers, feasibility on test hardware, recipes, process windows, matching between tools and the process data customers qualify on.
Discipline codes
Owns the hardware process assurance plan and the software quality assurance plan, audits that plans and standards are followed, transition criteria checks, conformity reviews and the quality system that production runs under.
Discipline codes
Defines what every product on the platform shares and where products may differ: the reference architecture, the variation points, the platform interfaces and the rules a derivative must follow.
Discipline codes
Defines the package structure and its targets from the customer drivers, compares options with the modelling team, sets the requirements for the test vehicles and reviews customer designs for chip, package and board fit.
Discipline codes
Writes the product specification from the test chip's silicon evidence, the design partners' needs and the product requirements, and supports it through to product tape-out.
Discipline codes
The development plan, the tool categories and flows the kit will support, the foundation IP plan and the maturity each release must reach are agreed and under change control.
Gate codes
In: PDK lifecycle
The integrated memory process is frozen as a baseline, with design rules and device models good enough for product design.
Gate codes
In: Memory lifecycle
The MEMS process flow is frozen with its design rules and control structures.
Gate codes
Pilot builds on the production line, with production test programs for chips, boards and finished devices, show the design can be built and tested consistently, and the results support process validation.
Gate codes
The project, risk, quality assurance, configuration and supplier plans are agreed, consistent with each other and baselined.
Gate codes
The integrated process is fixed in a baseline that prototype, characterisation and qualification wafers are built on, with its controls and known risks recorded.
Gate codes
Owns the sensor's business case, target applications, cost and pricing, sampling and customer commitments, and decides when to change, derive or withdraw it.
Discipline codes
Every pattern set the program needs exists in the tester's format and has passed simulation against the final netlist with tester timing, with the fault coverage it achieves recorded against the goal.
Gate codes
The pilot ran as planned, every output was checked against the known answer, and the results, failures and user feedback are reviewed to decide whether formal qualification is worth doing.
Gate codes
The construction and start-up project is closed: spend reconciled, as-built records handed over, incentive milestones reported, lessons recorded and the fab handed to operations.
Gate codes
In-house scans show margin to the regulatory limits and the standard's conformance requirements, so formal testing at an accredited laboratory can be booked with confidence.
Gate codes
In: RF lifecycle
Owns the business case, the customer requirements, the program plan, the certification plans and the liaison with the certification authority and the integrator, through the accomplishment summaries to in-service support and end of support.
Discipline codes
Plans the standards, schemes and markets, works with test laboratories, certification and notified bodies, and keeps certificates, declarations, the technical file and factory inspections current.
Discipline codes
Runs production to the control plans: statistical process control on special characteristics, reaction plans, layered process audits by every level of management, contingency plans and the total productive maintenance that keeps equipment capable.
Discipline codes
In: QMS lifecycle
A layout cell in a design kit that draws itself from parameters such as width and length.
Design and verification
Used in: PDK lifecycle: Layout Technology, PCells & Symbols, PDK lifecycle: Layout technology, PCells and symbols
The common high-speed serial interface between processors, accelerators, storage and other devices.
Devices and interfaces
Builds the layout technology file and layer map, the parameterised cells that draw devices correctly, and the schematic symbols and device parameters designers use.
Discipline codes
In: PDK lifecycle
A supplier's formal notice to customers that a product or its process will change.
Quality and reliabilityGate codes
Captures functional patterns from verification, converts every pattern set to the tester's format with its timing, simulates the converted patterns against the netlist and keeps pattern versions tied to netlist versions.
Discipline codes
What the platform shares and where products may differ are agreed: the products it serves, the common core, the planned variation points and what each derivative is expected to reuse.
Gate codes
Turns the full-chip netlist, with each IP block's physical views, into a manufacturable layout and closes timing, power and physical checks.
Discipline codes
In: SoC lifecycle
Implements the design for the mission profile and temperature grade, signs off electromigration, ageing and timing at the automotive corners, and keeps redundant logic physically apart where the safety analysis needs it.
Discipline codes
Floorplans and implements a large, power-dense die, plans the package with its high-bandwidth memory, closes timing and power integrity, and releases the database and package design to manufacture.
Discipline codes
Turns the test chip RTL into a database the shuttle accepts: flow and design kit trials, synthesis, test insertion, place and route, timing and physical sign-off, then correlation with silicon.
Discipline codes
Implements the layout with radiation rules, such as separation of redundant elements and latch-up structures, and signs off timing, power and reliability at the corners the dose budget sets.
Discipline codes
In: Space lifecycle
Assembles the full device layout from tiles, hard IP, clock and power networks and the input and output ring, closes timing and the physical checks, and tapes out each family member.
Discipline codes
The interposer or bridge and the substrate are routed and analysed together with the dies, and frozen: after this gate only fixes found by the multi-die sign-off are made, under change control.
Gate codes
The set of device models, rules, decks and libraries a foundry gives designers so their design can be built on its process.
Design and verification
Used in: PDK lifecycle, Process node lifecycle: PDK & Design Enablement Development, Process node lifecycle: Early access PDK release gate, Process node lifecycle: Design-start PDK release gate, Process node lifecycle: Pre-production PDK release gate, Process node lifecycle: Production PDK release gate, and 14 more
Builds and releases the process design kit in versions of rising maturity: models, design rule manual, verification and extraction decks and technology files, each release checked before it goes out.
Discipline codes
Brings the foundry's photonic design kit and the component library into the flow, fits and refreshes compact models from measured data, and keeps the verification decks the layout is checked with.
Discipline codes
Writes the assembly and substrate design rules, assembles the package design kit with stack-ups, models, libraries, checking decks and reference designs, releases it in versions and supports customers who design with it.
Discipline codes
The development part of a product's life, from concept to release for production.
Business and product lifecycle
Lays out the array tiles, the periphery and the interface, assembles the die, and runs physical verification, reliability checks and tape-out, with the shrink layouts that follow.
Discipline codes
In: Memory lifecycle
The discrete package or power module design, with its substrate, die attach, interconnect and cooling path, is released with its assembly process, so that qualification lots can be built in the target package.
Gate codes
Writes and verifies the product RTL from blocks fixed after the test chip, and roots out the cause of issues found on product silicon.
Discipline codes
A pilot project has used the processes and tools end to end, and what did not work has been fixed before wider rollout.
Gate codes
Owns the product on the test floor: first silicon results, correlation, the yield model and baseline, statistical bin limits, yield improvement and the lessons learned at end of life.
Discipline codes
Designs the chip, package and test to the agreed goals, leads the design FMEA and design reviews, runs design verification, releases specifications, drawings and the datasheet, and confirms the special characteristics.
Discipline codes
In: APQP lifecycle
Owns the die from first silicon onward: bring-up, characterisation across voltage, temperature and speed, the datasheet, debug of marginal behaviour, the bin and grade plan and the characterisation of shrinks.
Discipline codes
In: Memory lifecycle
Builds and maintains the analytical and simulation models that predict performance and efficiency, explores the design space with architecture and compiler teams, and correlates the model with silicon.
Discipline codes
Working out the unwanted resistance and capacitance of a layout's wires so timing and power can be checked.
Design and verification
Describes the interconnect stack in the interconnect technology file and extraction decks, and correlates extracted values with silicon test structure measurements.
Discipline codes
In: PDK lifecycle
Which function goes on which die, the node of each die and the packaging technology are fixed, so the interface, the dies and the package can start against one partitioning.
Gate codes
Before the architecture is frozen, the team shows that the photonic platform, the optical coupling and packaging approach, the laser integration approach and thermal control can meet the link budget, with the expected losses and limits stated.
Gate codes
The package, its environmental port or seal, its stress isolation and its assembly flow are frozen, with stress sensitivity shown to be inside the error budget.
Gate codes
The manufacturing route is designed and documented: process flow, process FMEA, pre-launch control plan, process instructions, the measurement system analysis plan and the capability study plan, packaging and labelling, so a production trial can be built on it.
Gate codes
In: APQP lifecycle
A large group of persistent chemicals, some used in chip manufacturing, now under reporting and restriction rules.
Export, trade and product law
Explores device architectures, materials, patterning and interconnect options with simulation and short experiments, and hands the chosen concept and what was learned to development.
Discipline codes
Plans and coordinates the development programme across hardware, software, process, supply and customers: the charter, plan and budget, the risk register, evaluation schedules, gate reviews, production readiness and the programme's lessons learned.
Discipline codes
Runs the cross-functional plan: the schedule, the dependencies between the engineering lifecycles and the business functions, the risk and issue lists, the gate reviews and their records.
Discipline codes
Owns the kit's scope, plan and releases: what each release must contain and how mature it must be, the release decision at each gate, and the kit's life to its end.
Discipline codes
In: PDK lifecycle
Owns the business case, the product plan and the gates: which application and customers the product serves, what it must cost, when it ships and when it is withdrawn.
Discipline codes
Runs the fab build as one programme: the master schedule, cost control, risk register, contracting strategy, interfaces between contractors, suppliers and the owner's teams, reporting, and the formal close-out and handover.
Discipline codes
Takes in each customer's requirements and FPGA prototype, quotes the design from the feasibility report and the platform's pricing model, agrees the statement of work, runs the customer programme through sign-off and samples, and keeps deliveries in step with the customer's demand.
Discipline codes
The part of an interface that drives and receives the electrical signals on the wire.
Devices and interfaces
The permits needed to start construction are granted, the path to operating permits is agreed, and the incentive agreements are signed with their conditions understood.
Gate codes
A chip that guides and processes light, such as lasers, modulators and detectors on one die.
Devices and interfaces
Used in: Photonics lifecycle
Designs the photonic integrated circuit: component targets, any custom components, the circuit and its simulation, thermal tuning, and correlation of the design with measured wafers.
Discipline codes
Builds the integrated memory process around the cell: high aspect ratio patterning and etch, capacitor or channel hole and stack formation, peripheral transistors and interconnect, and freezes the baseline, the design rules and later the shrinks.
Discipline codes
In: Memory lifecycle
Joins the modules into one assembly flow, owns the order of steps, the interactions between them and the full-flow test vehicle builds, and maintains the process baseline and its change log.
Discipline codes
Selects and licenses the product's IP on the test chip evidence and integrates the delivered IP into the product.
Discipline codes
A project starts on the released processes, with its tailoring approved by the process owner.
Gate codes
Selects and designs the package, often hermetic ceramic or a qualified non-hermetic alternative, owns the assembly drawings and materials, and qualifies the package to the agreed framework.
Discipline codes
In: Space lifecycle
Designs the package and the production test flow, and tests every part before it ships.
Discipline codes
In: SoC lifecycle
Designs the package or module and the fibre interface, develops die, laser and fibre attach with its alignment, manages the package's thermal and mechanical design, and builds the samples and qualification units.
Discipline codes
Designs and industrialises discrete packages and power modules: substrates, die attach by solder or sintering, wire bonds, clips or other top-side interconnect, encapsulation, baseplates and cooling interfaces, with low stray inductance and a reliable thermal path, the assembly line and its controls and later package cost-downs.
Discipline codes
Designs and qualifies the package that lets the environment reach the transducer, through ports, membranes, gels, windows or sealed cavities, with die attach and lid choices that keep package stress out of the signal.
Discipline codes
Designs the interposer, bridge or redistribution layers and the package substrate, runs the assembly-level checks across dies and package, and releases the package data with the dies.
Discipline codes
The equipment program is accepted, with a business case that allows for development assurance, certification liaison, qualification and support for the life of the aircraft, and a team is funded to define it.
Gate codes
The outputs of planning are reviewed and approved: design and reliability goals, quality goals, a preliminary bill of materials and process flow, the preliminary special characteristics, and a product assurance plan, so design can start against agreed targets.
Gate codes
In: APQP lifecycle
The life of a product from idea through launch, growth and maturity to end of life.
Business and product lifecycle
Used in: Product lifecycle
A circuit that generates a stable clock locked to a reference.
Devices and interfaces
Owns the platform business case, requirements and roadmap, the pricing and engineering charge model that each customer quotation is built from, production release and the end of the platform.
Discipline codes
The pilot line has qualified tools, released work instructions, trained operators, inline controls and known good die rules in place, so product-like lots can start.
Gate codes
Simulations rerun with extracted parasitics still meet the specification, and the reliability and ESD checks pass.
Gate codes
In: AMS lifecycle
The layout is clean and the extracted design, with electromagnetic models of the layout, meets the specification, so the die can be finished for tape-out.
Gate codes
In: RF lifecycle
Owns the product from concept to end of support: the product requirements, the roadmap fit, the business case after approval, the trade-offs between scope, cost and schedule, and every lifecycle decision.
Discipline codes
In: Product lifecycle, SoC lifecycle, FPGA lifecycle, System lifecycle
Owns the business case, the customer requirements, the development interface agreement with each customer, the mission profile and the long-term supply commitment.
Discipline codes
Owns the business case, the product requirements across silicon, system and software, the plan and the schedule, the early access and launch, the software roadmap after launch and the end of support.
Discipline codes
Owns what the software stack is for: the software requirements, roadmap, supported platforms, support period and release approvals, balancing customer needs against cost.
Discipline codes
Plans the adoption across projects, keeps the roadmap of AI-assisted steps, runs the first project plan and the transition when a step is retired, and reports adoption status.
Discipline codes
Owns the tool as a product: the customers' process roadmaps it serves, the market and competitive view, the business case including service and upgrades, pricing and configurations, the choice of evaluation customers, and the platform's lifecycle decisions.
Discipline codes
Owns the business case, the device concept, the design and development plan and schedule, launch readiness and the supply and support commitments, and leads discontinuance with customers and service teams.
Discipline codes
Owns the business case, the application profile, the program plan, the datasheet and the long-term supply commitment, and leads end-of-support decisions with customers.
Discipline codes
Plans and runs each project on the tailored process: scope, estimates, schedule, resources, interfaces and commitments, the risk register and its treatments, and progress reporting, adjusting the plan when reality moves.
Discipline codes
Leads the cross-functional team, owns the quality planning timing chart against the customer's program milestones, runs the phase reviews with management, tracks open issues and keeps the customer informed of status.
Discipline codes
In: APQP lifecycle
Owns why the platform exists and whether it pays: the business case across the product family, the roadmap, approval of derivatives, roadmap reviews and the platform's retirement.
Discipline codes
Owns the market view: segments, customer needs, competitors, positioning, pricing input and the launch, and keeps the product's message current through its life.
Discipline codes
Keeps a small team moving in one direction: the operating plan, the test chip and product plans, the risk register, hiring, the tape-out checklist, and the quality system a production customer expects.
Discipline codes
The process group that defines, maintains and improves the standard processes, templates and tailoring guideline, trains and coaches the teams, and turns assessment findings into improvement actions.
Discipline codes
Each owner designs, runs and measures one process of the system, such as product realisation, purchasing, production, test, logistics or design, keeps its documentation current and answers audit findings for it.
Discipline codes
In: QMS lifecycle
Runs the product's outsourced manufacturing chain: production node, unit cost and supply plan, mask and wafer orders, the first build, packaging and test suppliers, and supply resilience.
Discipline codes
Target market, cost, schedule and feature set are agreed between the business and engineering.
Gate codes
In: SoC lifecycle, AI accelerator lifecycle, Memory lifecycle, RF lifecycle, FPGA chip lifecycle
A design kit with models correlated to silicon across corners and rules near final lets customers design products for tape-out, at an agreed and stated risk.
Gate codes
The platform hardware runs its software at speed on emulation and FPGA prototypes, and the conformance tests pass on them.
Gate codes
The array sizes to build first, the design kit scope, the pricing and engineering charge model, cost and schedule are agreed between the business and engineering, and development of the platform is committed.
Gate codes
The three measures a chip design is usually judged and traded off on.
Design and verification
Sets performance and power targets from the architecture and tracks them through RTL, emulation and physical design to correlation on silicon.
Discipline codes
In: SoC lifecycle
The automotive process in which a supplier shows, with records, that its production process makes parts that meet requirements.
Quality and reliabilityStandards and regulations
Used in: PPAP guide, Traceability overlay, Automotive lifecycle: Automotive quality and PPAP, APQP lifecycle: PPAP Submission & Approval, APQP lifecycle: PPAP submitted gate, APQP lifecycle: PPAP approved gate
Implements the product on the production node: floorplan and trials from the test chip correlation, then synthesis, test insertion, place and route, timing, power and physical sign-off.
Discipline codes
Owns the power product as a business: target applications and customers, the choice between silicon, silicon carbide and gallium nitride, the business case and pricing, the roadmap of voltage classes and generations, the datasheet, the supply commitment and the decision to discontinue.
Discipline codes
A kit with models correlated across corners, rules near final and characterised libraries lets customers design products for tape-out at an agreed and stated risk.
Gate codes
In: PDK lifecycle
The process at the new fab is shown to match its reference in results, yield trend and reliability, and is released for customer product wafers.
Gate codes
Key injection, device identity, lifecycle locking and supply chain controls are proven at every production site before production parts carry secrets.
Gate codes
A customer qualifies the tool in its process and releases it into its process baseline, and the configuration that was qualified is recorded with an agreed change notification arrangement.
Gate codes
The assembled multi-die package has passed qualification to the agreed standard on units from the production assembly and test flow, with every failure analysed, and the final test program is released, so the product can move to production release.
Gate codes
Plans the package qualification from the sign-off results, qualifies the package under temperature cycling, moisture and other stresses, and analyses failures in bonds, bumps and interposer.
Discipline codes
Qualification has passed, the datasheet and production test program are released, supply is ready and the part is released for volume orders.
Gate codes
In: Product lifecycle, SoC lifecycle, AMS lifecycle, Chiplet lifecycle, FPGA lifecycle, Automotive lifecycle, AI accelerator lifecycle, Startup lifecycle, Memory lifecycle, Photonics lifecycle, MEMS and sensors lifecycle, RF lifecycle, Equipment lifecycle, Medical lifecycle, Industrial lifecycle, System lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
The production design kit, with final models and rules correlated to risk production silicon and validated sign-off decks, is released for production tape-outs.
Gate codes
The production software is released with production-signed images, the SDK, documentation, the software bill of materials and licence compliance, and the update service is ready.
Gate codes
The step is released in the production flow for every team within its qualified scope, with controlled documentation, training, capacity and an approved production environment.
Gate codes
Qualification has passed, customers have approved the part for production, for automotive through the production part approval process, and the part is released for volume orders with a supply commitment.
Gate codes
Before the security release, a public way to report vulnerabilities, a disclosure policy and a staffed incident response procedure are in place for the product.
Gate codes
The standard process set, tools and training are released for use by every project in scope.
Gate codes
The item is approved to leave development: production controls protect it, keys are provisioned securely, and monitoring, incident response and updates are ready.
Gate codes
A periodic review shows the certified system is performing: customer scorecards, problem solving closure, layered process audits, contingency plan tests and improvement projects are on track.
Gate codes
In: QMS lifecycle
Owns production transition, manufacturing and test procedures, first article inspection, production test correlation with qualification, and the production release of conforming units.
Discipline codes
Designs the manufacturing route across wafer fab, bump, assembly and test sites: process flow, process instructions, line layout, equipment and tooling, and leads the process FMEA with quality engineering.
Discipline codes
In: APQP lifecycle
The array sizes, the fixed blocks, the customisable layers, the target turnaround and the kinds of designs the platform must carry, including FPGA conversions, are written down and agreed.
Gate codes
Specifies, designs, orders, checks out and maintains the probe cards for wafer sort, including their planarity, contact and cleaning practice, and plans spares for the life of the product.
Discipline codes
List prices, volume pricing rules, channel margins and the ordering information are approved against the standard cost, ready for publication at the launch review, so quotes and the launch price list rest on the margin the business agreed.
Gate codes
Brings the process into the kit: device targets and design rule intent from the technology definition, baseline silicon and test structure measurements, and qualification results and process changes later.
Discipline codes
In: PDK lifecycle
Develops and integrates the wafer process: implantation and activation, gate oxide and interface treatment, trench etch where used, ohmic and Schottky contacts, passivation and field plates for gallium nitride, thinning and backside metal, and transfers the process to larger wafers and qualifies later process changes.
Discipline codes
Sources the tools and materials: long-lead orders, purchase specifications and acceptance terms, supplier risk and single sources, export control classification and licences for tools and technology, materials declarations such as RoHS and REACH, delivery logistics, and the supply agreements and supplier reviews the running fab depends on.
Discipline codes
Develops, freezes and sustains the MEMS process: films and their stress, deep etching, release, anti-stiction treatment, bonding and cavity sealing, with the design rules and control structures, and qualifies process changes.
Discipline codes
Product RTL is feature complete; only fixes go in from here.
Gate codes
Builds the evidence before silicon: the FPGA or emulator prototype and the demo investors and partners see, then a prototype platform that lets software and test chip logic run early.
Discipline codes
Models, rules, decks and libraries are final pending process qualification, the open errata from pre-production design starts are closed or scheduled, and the production release can be planned.
Gate codes
In: PDK lifecycle
Timing, power and physical checks are clean on the final layout, and the layout matches the netlist.
Gate codes
Enough early money, from founders, angels, a grant or an accelerator programme, is committed to pay for the proof of concept, with what it must show agreed in advance.
Gate codes
The fab starts product wafers for customers, with its quality system certified, operations ready and customers qualifying their products.
Gate codes
A recurring review of complaints, vigilance reports, trends, vulnerability findings, field actions and changes confirms the benefit-risk balance still holds, updates the risk management file and decides any corrective action or design change.
Gate codes
The certification plans and the plans and standards under them are complete, consistent with each other, submitted to the certification authority or the integrator, and reviewed at the first stage of involvement.
Gate codes
The production part approval package is complete at the required submission level, every element has been checked against the customer specific requirements, the part submission warrant is signed and the package is submitted.
Gate codes
In: APQP lifecycle
Firmware and the main software run on emulation or FPGA prototypes of the hardware, the main use cases have been exercised, and the hardware and software issues found are tracked to closure.
Gate codes
In: System lifecycle
Owns the product's security: the security plan and secure development lifecycle, the review board, the release decision, residual risk acceptance and the security support plan until the end of support.
Discipline codes
Plans and runs post-market surveillance: complaint handling, trend analysis, vigilance reporting, field safety corrective actions, periodic reports, component obsolescence watch and the records archive at end of support.
Discipline codes
Protects the item in production: the cybersecurity control plan, secure provisioning of keys and certificates, end-of-line configuration and locking, protection of production tools and data, and the release for post-development.
Discipline codes
Leads disciplined problem solving for customer complaints, internal escapes and audit findings: containment, root cause by occurrence and escape, corrective and systemic preventive action, verification and closure, and the warranty and returns analysis that feeds it.
Discipline codes
In: QMS lifecycle
Owns the threat model, the security architecture, secure boot and update, security testing, the software bill of materials and the response to vulnerabilities until the end of support.
Discipline codes
In: System lifecycle
The product's requirements and specification are fixed, with the production node, package, IP and test strategy chosen and the unit cost model agreed, so product silicon design can be planned and funded.
Gate codes
The team that receives vulnerability reports about products and coordinates fixes and disclosure.
Safety and security
The partners for first silicon are chosen and the key agreements signed: foundry and process for the test chip, EDA licences and compute, third-party IP, design services where used, and packaging and test, with the build or partner choice recorded for each.
Gate codes
The frozen product chip has passed verification, test and physical sign-off on the production process, so the full mask set can be ordered.
Gate codes
The layout and the views characterised across corners are released to SoC teams that accept the silicon risk, with release notes that state it.
Gate codes
The compiler, runtime, drivers and libraries run the target workloads end to end on emulation or a prototype, so hardware problems found by software are fixed before tape-out.
Gate codes
Boot code, key firmware and drivers run on the virtual platform and on emulation of the frozen RTL, the bring-up plan is written, and software tests have been run on the design before tape-out.
Gate codes
Owns the product definition: the bands, standards and markets it serves, the business case and product plan, and the commercial side of release, sustaining and end of life.
Discipline codes
In: RF lifecycle
Writes the firmware, drivers and software development kit that ship with the product, first on the prototype platform and then on product silicon, and maintains them.
Discipline codes
The performance model predicts that a candidate design meets the throughput, latency, efficiency and accuracy goals on the target workloads, and those goals are baselined.
Gate codes
The signed-off product database has been released on the production process and the full mask set ordered, with packaging, test, boards and software ready for first silicon.
Gate codes
Sets the RF test strategy, builds the test program and test hardware, correlates tester results to the bench, sets production limits and reduces test time.
Discipline codes
In: RF lifecycle
Chooses the product package and test strategy from the test chip experience, designs the package, develops the test program and qualifies the product through outsourced assembly and test suppliers.
Discipline codes
Plans how the process reaches the new fab, transfers recipes and specifications, matches tools to their references, runs the first wafers, qualifies the process and puts process control in place, then owns process changes in operation.
Discipline codes
Before the AMS specification is frozen, the team shows that the chosen process and devices can deliver the performance targets: the device models are accurate enough for the critical circuits, and the riskiest circuits are shown feasible on the target process.
Gate codes
In: AMS lifecycle
The test program, its hardware, limits, flows and operator instructions are released for volume production under change control, with the test quality sign-off in place.
Gate codes
A recurring decision: each update to the design kit, the base process or the supply chain is assessed for its effect on customer devices already built on the platform before it is released, and customers are notified.
Gate codes
Measured performance and efficiency on the target workloads are compared with the targets and the model, and the remaining gaps have owners and plans.
Gate codes
Design partners have evaluated the test chip or platform on their own problems and stated in writing what value they saw, what they need changed and whether they intend to buy the product.
Gate codes
The production trial has shown that the process meets its requirements at rate: measurement systems are acceptable, initial capability on special characteristics meets the customer's requirement, production validation and qualification tests are passed, packaging is evaluated and the production control plan is approved.
Gate codes
In: APQP lifecycle
Units built on the production line, with production tooling, test and suppliers, meet the requirements and the target yield, so the system is ready for production release.
Gate codes
In: System lifecycle
Codes the rules as design rule check, layout versus schematic, antenna, density and electrical rule check decks for each supported tool category, and proves each check on pass and fail test layouts.
Discipline codes
In: PDK lifecycle
Verifies the platform as a whole and owns the conformance test suite every derivative must pass to stay on the platform.
Discipline codes
Designs the product evaluation boards, brings up product silicon, validates it against the specification, writes the errata and the datasheet and builds the evaluation kits customers use.
Discipline codes
The circuit meets its specification across corners and Monte Carlo runs, and works with the surrounding digital logic in mixed-signal simulation.
Gate codes
In: AMS lifecycle
The customer has approved the part for production shipment, either fully or with an interim approval whose conditions and expiry are recorded and tracked.
Gate codes
In: APQP lifecycle
The checks and reviews that show a product or a kit meets its requirements before release.
Quality and reliabilityDiscipline codes
Runs advanced product quality planning under IATF 16949, the design and process FMEAs, the control plan and the production part approval submission, and keeps statistical process control running in production.
Discipline codes
Checks the kit as a whole: a library of QA test cases and QA designs run through every supported tool category, regression on every change, and the checks that the parts of the kit agree.
Discipline codes
In: PDK lifecycle
Assesses how much confidence the tool needs and how its errors would be detected, writes the human review policy, controls the flow documentation, runs incident and corrective action handling and change impact assessment, and records lessons learned.
Discipline codes
Defines the screening flow and lot acceptance tests, plans and runs qualification to the agreed framework, and reports lot acceptance for every flight lot.
Discipline codes
In: Space lifecycle
The equipment has passed the environmental and electromagnetic qualification tests in its specification, with deviations dispositioned, and the reliability and derating analyses support the safety assessment.
Gate codes
Quality planning for the part is closed: process performance meets the goals, customer feedback is acted on, and lessons learned are recorded and fed into the next program.
Gate codes
In: APQP lifecycle
Sets and audits the software process: the quality plan, coding standard, static analysis and coverage rules, licence compliance for third-party and open-source code, and the process and safety evidence some markets require.
Discipline codes
Keeps the tool's configuration known and controlled: design reviews, configuration baselines from alpha onward, the record of what each customer qualified, change notification agreements, field change orders and customer change notices, corrective actions and the final archive.
Discipline codes
Sets the quality plan, runs process failure mode analysis, keeps the materials declarations and the RoHS, REACH and export control compliance file, controls changes to the frozen baseline, manages customer quality agreements and audits, and issues change and discontinuance notices.
Discipline codes
The customer device is qualified, largely by similarity to the qualified base array with any device specific tests the qualification family definition calls for, and the production test program is released.
Gate codes
Facilitates the FMEAs with the engineering teams, keeps the process flow, PFMEA and control plan consistent, writes the prototype, pre-launch and production control plans with their reaction plans, and runs the capability studies.
Discipline codes
In: APQP lifecycle
The part, package and line pass qualification to the agreed framework, and the qualification report and radiation hardness assurance report are approved.
Gate codes
In: Space lifecycle
Parts and modules built on the intended production flow enter reliability qualification.
Gate codes
In: RF lifecycle
Plans product quality, prepares production part approval and the control plan where customers need them, runs field return analysis and corrective action, and issues change and discontinuance notices.
Discipline codes
Runs the quality management system the design sits in: design control procedures, document and record control, design reviews, supplier and purchasing controls, the design history file and device master record, internal audits, CAPA and management review.
Discipline codes
Runs the system day to day for top management: context analysis, gap assessment, the implementation plan, the risks and opportunities register, objectives tracking, certification body liaison and the transition to revised standards.
Discipline codes
In: QMS lifecycle
The list of makers qualified to supply integrated circuits to the US defence specification.
Quality and reliability
An organisation's documented system for planning, controlling and improving quality.
Quality and reliability
Used in: QMS lifecycle, QMS lifecycle: Gap Assessment & QMS Planning, QMS lifecycle: QMS plan approved gate
Every stress test in the qualification plan has passed on parts from the production flow, or has an approved disposition, to the standard each target market expects, such as JEDEC or AEC-Q100.
Gate codes
In: Product lifecycle, SoC lifecycle, AMS lifecycle, AI accelerator lifecycle, Startup lifecycle, MEMS and sensors lifecycle, RF lifecycle, FPGA chip lifecycle
The gap assessment is complete and the plan to close it is approved, with objectives, risks and opportunities, owners, resources and the certification timing.
Gate codes
In: QMS lifecycle
The program that tests the qualification lots before and after stress is released, so qualification results reflect the production screen.
Gate codes
Sets the quality and reliability targets for the intended markets, plans and runs qualification, keeps the product in the quality system, and analyses field returns and changes for as long as parts are in service.
Discipline codes
In: Product lifecycle, SoC lifecycle, RF lifecycle, FPGA chip lifecycle
Sets the reliability requirements and the qualification plan for the base array, and agrees the family rules by which customer devices are qualified largely by similarity to it.
Discipline codes
Parts built on the intended production flow, from the lots and sites the qualification plan names, are available for the supplier's own qualification and for the customers who run their own.
Gate codes
Parts built on the intended production flow enter qualification testing.
Gate codes
In: SoC lifecycle, Automotive lifecycle, MEMS and sensors lifecycle, FPGA chip lifecycle
Parts built on the intended production flow enter qualification testing against an approved plan.
Gate codes
In: Product lifecycle, Photonics lifecycle, Power and compound lifecycle
Runs advanced product quality planning, design and process FMEAs, the compliance register for qualification standards, RoHS, REACH and export classification, customer-specific requirements, audits and the production part approval process, field monitoring and returns analysis, process change notices to customers and the records kept to the end of supply.
Discipline codes
Plans and runs AEC-Q100 qualification for the temperature grade, with ESD and latch-up, package and life tests, and drives failure analysis on any part that fails.
Discipline codes
Sets up the quality management system, plans yield learning, sets the defect baseline, qualifies process reliability, supports customer product qualification and certification, and drives yield and quality in operation.
Discipline codes
The software requirements, the supported platforms, the support period and the quality plan are agreed with product management and engineering.
Gate codes
A memory generation, its density points and the interface standards it will follow are put on the roadmap, and a team is funded to define it.
Gate codes
In: Memory lifecycle
The mission profile, voltage class, current rating, switching conditions, ruggedness needs and target cost are agreed with the business and lead customers and baselined as the product requirements.
Gate codes
A new package technology is placed on the packaging roadmap, with the customer drivers behind it, and a development team is funded to define it.
Gate codes
The product may ship from a security point of view: requirements met or risks accepted, certificates and declarations in place, provisioning running, incident response ready and customers given what they need to integrate it securely.
Gate codes
Hazards and threats are analysed, the risk reduction the product must provide is decided, and the target integrity and security levels are agreed with the customer or the system owner.
Gate codes
The platform roadmap, the lead product and the first derivatives, with their cost, schedule and resources, are agreed and the platform's development is committed.
Gate codes
Classifies the device in each market, sets the regulatory strategy and applicable standards, prepares technical documentation and submissions, deals with notified bodies and authorities, and assesses every later change for its regulatory effect.
Discipline codes
The four properties railway systems are specified and shown to meet.
Safety and securityStandards and regulations
Used in: EN 50126 guide
The mission profile, radiation environment and quality level are agreed with the customer and baselined, so every later design and test decision can be traced to them.
Gate codes
In: Space lifecycle
The sensing specification and the environmental and mission profile are agreed and placed under change control, so transducer, process and ASIC work design to the same targets.
Gate codes
The RF requirements are baselined: every band, power, sensitivity, linearity, efficiency and coexistence target is written with how it will be verified, and the regulatory regimes of each market are known.
Gate codes
In: RF lifecycle
Security requirements are written from the threat model, each traced to its threat and to the verification that will prove it, and placed under change control.
Gate codes
The process, performance, productivity, cost, safety and factory interface requirements are written, traced to customer needs and agreed as the baseline for concept work.
Gate codes
Hardware and software requirements are complete, traced to the system requirements, validated, and under configuration control; derived requirements have been reviewed by the safety assessment.
Gate codes
In: Avionics lifecycle, Industrial lifecycle, Automotive SPICE lifecycle
The system requirements and use cases are reviewed and placed under change control, so architecture, hardware and software teams work to one agreed set.
Gate codes
In: System lifecycle
Specifies and delivers the reference and evaluation boards the software is brought up, validated and shipped on, with their debug access, power measurement points and board files.
Discipline codes
The product runs at a steady state: yield and cost are at or near plan, delivery is reliable, early field issues are closed or contained, and sustaining owners take over.
Gate codes
In: Product lifecycle, Process node lifecycle, Memory lifecycle, Power and compound lifecycle, Fab build lifecycle, MEMS and sensors lifecycle, Package technology lifecycle, Structured ASIC lifecycle
Users have moved off the step, data held by the supplier is deleted or returned with confirmation, licences are closed and the records needed to reproduce past results are archived.
Gate codes
The part's radiation response is measured and reported, compared with the predictions, and the hardness level the part can be supplied to is agreed.
Gate codes
In: Space lifecycle
A tool programme is opened against named customer technology roadmaps, with a sponsor, a core team and funding to define requirements.
Gate codes
The recertification audit is complete before the certificate expires, any transition to a revised standard is done, and a renewed certificate is issued.
Gate codes
In: QMS lifecycle
Works out which security regulations and export rules apply in each market, classifies the cryptographic functions for export, prepares the conformity evidence and declarations, and keeps reporting obligations in the field.
Discipline codes
The owner decides to retire or replace the step, with the reason recorded, a transition plan for its users and a fallback or replacement flow ready.
Gate codes
Extra wiring layers that reroute a die's connections to where the package needs them.
Manufacturing, test and packaging
Used in: Package technology lifecycle: Wafer-level processes: bumping, RDL and fan-out
Owns the radiation environment specification, the technology radiation assessment, the hardening approach, the dose budget, the single-event rate predictions and the radiation hardness assurance plan and report that tie design, test and lot acceptance together.
Discipline codes
In: Space lifecycle
Plans and runs the reliability and qualification work: the design verification plan's stress tests, the qualification plan against AEC-Q100, AEC-Q101, AEC-Q104 or AEC-Q200 as applies, mission profile review, and requalification after changes.
Discipline codes
In: APQP lifecycle
The EU regulation on chemicals, including the list of substances of very high concern.
Export, trade and product law
Used in: RoHS, REACH and WEEE guide, Interoperability and compliance overlay
Plans and runs the intrinsic reliability tests, analyses every failure, writes the technology qualification, and runs reliability monitoring and change qualification once the node is in volume.
Discipline codes
Writes how devices and wires age and fail into the kit: ageing and self-heating models, electromigration and current density rules, and the ESD and latch-up rules, from the process reliability data.
Discipline codes
In: PDK lifecycle
Assesses cell and product reliability from test vehicles on, plans and runs component qualification and conformance testing to JEDEC methods, issues materials declarations such as RoHS and REACH, handles customer quality and returns, and requalifies shrinks and changes.
Discipline codes
Sets reliability requirements from the mission profile and proves them: gate oxide lifetime, threshold drift, blocking and humidity stresses, temperature and power cycling, body diode degradation, avalanche, short-circuit and cosmic ray robustness, failure analysis, lifetime models, module qualification and requalification of later changes.
Discipline codes
Sets reliability requirements from the mission profile, runs early stress on prototypes, plans and runs qualification for the MEMS, ASIC and package together, analyses every failure, and monitors reliability in volume.
Discipline codes
Plans and runs component-level and board-level reliability tests, analyses every failure with the failure analysis lab, writes the technology qualification report and supports customers' product qualifications.
Discipline codes
Circuits and signals at the frequencies used for wireless links and radar.
Design and verification
Used in: RF lifecycle, AMS lifecycle: RF and millimetre-wave design, Test program lifecycle: Analog, mixed-signal and RF test, RF lifecycle: RF Characterisation & S-parameter Measurement, RF lifecycle: Post-layout RF sign-off gate, RF lifecycle: RF system architecture and link budget, and 6 more
Designs the reference boards and the lead product's hardware that prove the platform on silicon, and publishes reference designs that derivative teams start from.
Discipline codes
Runs risk management to ISO 14971 across the whole life: the plan and acceptability criteria, hazard analysis, risk evaluation, risk control selection and verification, overall residual risk and benefit-risk, the risk management report and updates from production and field data.
Discipline codes
Tool building reaches repeatable quality and cycle time, with build issues closed and the standard cost known.
Gate codes
Product teams and customers are told no new derivatives will start on the platform, when support will end, and how to move to its successor.
Gate codes
The EU law that limits named hazardous substances in electrical and electronic equipment.
Export, trade and product law
Used in: RoHS, REACH and WEEE guide, Interoperability and compliance overlay
Memory whose contents are fixed at manufacture, such as the boot code a chip runs first.
Design and verification
Used in: Firmware and software lifecycle: Boot ROM & Secure Boot Chain, Firmware and software lifecycle: Boot ROM freeze gate, Firmware and software lifecycle: Boot ROM
Customer product wafers start on the qualified process under agreements that state the remaining risk, with tools, materials and capacity ready for the first volumes.
Gate codes
The product requirements turn the market requirements into measurable, testable requirements that engineering agrees it can meet, and are baselined so the specifications and the plan are built on them; the development commit confirms the baseline.
Gate codes
The reliability stresses the macro needs have passed on test chips to the agreed plan, so the macro is technically ready for production use.
Gate codes
A changed tool, model, setting, hosting arrangement or set of terms has been assessed, the affected evidence rerun, and the updated step approved for release.
Gate codes
A change to the product or process has been assessed, notified where required, requalified by the agreed plan and approved by the customer where required, so it can be implemented.
Gate codes
In: APQP lifecycle
A periodic review decides whether to keep investing in the node, start a derivative or enhanced version, reduce cost, or plan its phase-down.
Gate codes
The radiation test plan, test boards, samples and facility time are ready, and the hardness assurance plan says what each test must show.
Gate codes
In: Space lifecycle
Reported vulnerabilities are triaged, fixed or mitigated and disclosed as agreed, and the lessons are fed back into the threat model and the next product.
Gate codes
The platform's use, cost, support load and technical debt are reviewed against plan, and the team decides whether to extend it, start its next version or plan its retirement.
Gate codes
Sets and proves reliability targets and uptime measured in line with SEMI E10, leads hazard analysis and safety assessment against SEMI S2 and SEMI S8 guidance, prepares the regional conformity files the tool needs, and follows field reliability once tools ship.
Discipline codes
Writes the firmware on the accelerator, the kernel driver and the runtime that loads programs, manages memory, schedules work and reports telemetry, and keeps them working across operating system and framework updates.
Discipline codes
Plans and runs the radiation test campaigns: total dose with in-situ or before-and-after measurements, single-event testing at heavy ion and proton facilities, and displacement damage where relevant, and reports the results.
Discipline codes
In: Space lifecycle
The US aviation body that publishes DO-254 and DO-178C; the letters first stood for Radio Technical Commission for Aeronautics.
Standards bodies and agencies
The level at which digital logic is described in a hardware language, as registers and the logic between them.
Design and verification
Used in: SoC lifecycle: SoC RTL Design, SoC lifecycle: RTL freeze gate, SoC lifecycle: SoC RTL design, Soft IP lifecycle: RTL to Early Access, Soft IP lifecycle: RTL Completion, Soft IP lifecycle: IP RTL freeze gate, and 10 more
Writes the full-chip design code around the IP blocks: the top level, the glue logic and the chip's own blocks.
Discipline codes
In: SoC lifecycle
Writes the design code for the compute arrays, on-chip memories, memory controllers, network on chip and interfaces, and fixes the bugs verification and pre-silicon software find.
Discipline codes
Suppliers for every die, the interposer, the substrate, assembly and test are agreed, with their quality expectations.
Gate codes
The kit for the node is approved and funded: which devices, options, design styles and customers it serves, and who owns it.
Gate codes
In: PDK lifecycle
The round that pays for product silicon is signed and received, with a development plan, budget and runway that reach first revenue, and a board that has approved the product plan.
Gate codes
A shrink, a layer or bits per cell step, or a derivative is approved with its cost per bit case and its requalification scope.
Gate codes
In: Memory lifecycle
The starting material is specified and at least one qualified source, internal or external, is committed in the volumes and at the quality the plan needs.
Gate codes
The overall scope, the application profile, the certification schemes and markets, and the plans for functional safety and security management are agreed, so every later activity has an owner and a standard.
Gate codes
The processes in scope, the target capability level for each, the organisational unit, the projects, the plug-ins and the model version are agreed with the sponsor and, where the customer requires it, with the customer.
Gate codes
The scope of the system, its sites and remote support functions, the products and the standards applied are agreed, with the quality policy and the register of customer specific requirements.
Gate codes
In: QMS lifecycle
Designs the software stack and agrees the hardware-software interface with the chip architects: memory map, registers, interrupts, the split between boot ROM, firmware and drivers, and the change control that keeps both sides aligned.
Discipline codes
Designs the root of trust, secure boot chain, key storage, isolation and lifecycle states from the security requirements, allocating every requirement to an architecture element and keeping the security architecture in step with the chip architecture.
Discipline codes
Carries out the quantitative and qualitative safety analyses: the safety concept, FMEDA and hardware metrics, dependent and common cause failures, and the safety manual's conditions of use.
Discipline codes
Decides how the system is built: its block structure, the chips and modules it uses, which functions go into silicon, programmable logic, firmware or software, and the interfaces between them.
Discipline codes
In: System lifecycle
The FMEDA, fault tree and dependent failure analyses are complete on the frozen design, and the hardware architectural metrics meet the targets for the ASIL.
Gate codes
The engineering body that publishes automotive and aerospace standards; the letters first stood for Society of Automotive Engineers.
Standards bodies and agencies
Used in: ISO/SAE 21434 guide, Security overlay, Obsolescence management overlay, Traceability overlay, AI governance overlay
The SAE standard for avoiding, detecting, mitigating and disposing of counterfeit electronic parts.
Standards and regulations
Used in: Obsolescence management overlay
Finds and qualifies the customers, brings their needs into the concept, wins designs during sampling, turns design wins into orders and forecasts, and manages the accounts through to the last-time buy.
Discipline codes
Splits the product between FPGA logic, processors and software, chooses the device, and writes the architecture the logic and board teams build from.
Discipline codes
In: FPGA lifecycle
The technical documentation or premarket submission is complete, internally reviewed and consistent with the design history file, and the quality system is ready for any audit the route requires.
Gate codes
A list of the software components and versions inside a product, used to track vulnerabilities.
Safety and security
Bench measurements across conditions are explained against simulation, and the device models are updated where they differ.
Gate codes
In: AMS lifecycle
The seed round is signed and the money received, with a plan and runway that reach test chip results and the next round, and the board and reporting set up that investors expect.
Gate codes
The part has been measured against its specification with fixture effects removed, and measurements agree with simulation closely enough to trust the models, or every difference is explained and recorded.
Gate codes
In: RF lifecycle
Support ends as announced: last-time-buy orders are filled, open service commitments are closed, and design and service records are archived for as long as they must be kept.
Gate codes
A surveillance audit is complete and any nonconformities are closed, so the certificate stays valid until the next audit.
Gate codes
In: QMS lifecycle
The fabric and the hard IP have been measured across voltage, temperature and process corners, and the measured delays have been compared with the pre-silicon timing models.
Gate codes
Owns the threat model, the security architecture of the software stack, secure boot and secure update, the signing service and key management, and the security review before release.
Discipline codes
Secures the path from design data to the customer: IP and component provenance, protected mask and test data, key generation and injection, device identity and certificates, lifecycle locking and counterfeit prevention at every site.
Discipline codes
Owns the platform threat model and security architecture, reviews reused IP, and answers for vulnerabilities across every product that shares the platform until its end of support.
Discipline codes
The functional and technical safety concepts are approved and the hardware safety requirements are baselined, so the architecture and design can be built against them.
Gate codes
Plans and allocates substrate, epitaxy, wafer fab and assembly capacity, models cost per die and per module, builds the business case for wafer size moves and second sources, runs the cost-down programme and the last-time-buy and final builds.
Discipline codes
Chooses and contracts the wafer, assembly and test suppliers, plans demand and capacity, makes production ready, runs the ramp and steady-state supply, and plans the final builds and any bridge supply at end of life.
Discipline codes
Qualifies substrate and material suppliers, plans capacity across tools and sites, secures long-term supply agreements for volume, tracks supply risk and plans the run-out of materials at end of life.
Discipline codes
For stacked products such as HBM, the stack architecture, base die interface, through-silicon via plan and bump map are frozen as product design starts, before the core and base die designs close, so the package and interposer partners can design against them.
Gate codes
In: Memory lifecycle
Packages what customers develop with: compiler toolchain and debugger support for the chip's cores, the SDK libraries, headers and examples, middleware, connectivity stacks and reference applications.
Discipline codes
The compilers, libraries, drivers and examples that let developers write software for a chip.
Design and verification
Used in: Firmware and software lifecycle: SDK, Toolchains & Reference Software, Firmware and software lifecycle: Early-access SDK gate, Firmware and software lifecycle: SDK, toolchains and reference software, Platform lifecycle: Tools, SDK and build infrastructure
The schematics and their simulation results at nominal conditions and the main corners are reviewed by peers before full verification starts.
Gate codes
In: AMS lifecycle
Each subsystem design is reviewed against its specification with test stand results, its design FMEA and its interfaces, and released for the prototype build.
Gate codes
The silicon has been attacked as the threat model expects an attacker would, protocol interoperability is shown, and every weakness found is fixed, mitigated or recorded as accepted security errata.
Gate codes
Defines the item or its out-of-context assumptions, carries out the hazard analysis, writes the safety concepts and hardware safety requirements, and runs the FMEDA, fault tree and dependent failure analyses.
Discipline codes
Owns the requirements and how the tool meets them: the system architecture, the split into subsystems, the interfaces between them, the performance error budget, the cost of ownership model and requirements traceability from customer need to test evidence.
Discipline codes
Turns user needs into design inputs, owns the system architecture, interfaces and essential performance definition, keeps the trace from user needs to design outputs and verification, and writes the design verification report.
Discipline codes
Runs the secure development process and the security risk work: threat and risk assessment, security requirements and architecture, security verification, user guidance, vulnerability handling and security updates for the support period.
Discipline codes
Elicits stakeholder requirements, derives and analyses system requirements, designs the system architecture and allocates requirements to hardware and software, integrates and verifies the system, and keeps traceability from stakeholder needs to system tests.
Discipline codes
Protects the design in the field: bitstream encryption and authentication, key provisioning in production, and a safe route for field updates.
Discipline codes
In: FPGA lifecycle
Classifies the design data involved, approves what may go where for the pilot and for production, assesses the supplier's hosting and access controls, sets up the environments and confirms deletion at retirement.
Discipline codes
The global association of the semiconductor equipment and materials supply chain, which publishes SEMI standards.
Standards bodies and agencies
Used in: SEMI S2 and SEMI S8 guide
A part developed for safety use before the vehicle it will go into is known, on stated assumptions.
Safety and security
The circuit that turns parallel data into a fast serial stream and back, the core of high-speed links.
Devices and interfaces
The engineering specifications of the product, such as the chip architecture specification, are frozen against the approved product requirements, so the cost, power and schedule the plan commits to rest on a baselined design intent.
Gate codes
The screening every flight part goes through and the lot acceptance tests for each lot are defined, proven on real lots and approved by product assurance and the customer where required.
Gate codes
In: Space lifecycle
Every planned firmware and software feature is in the build and tested on models or prototypes, and the secure update design is ready, so integration on real hardware can focus on fixes.
Gate codes
In: System lifecycle
The speed grades and temperature grades are set from characterisation and production silicon, the binning tests sort parts into them, and the design software is released with production timing data for each grade.
Gate codes
The hazard analysis is complete and confirmed, and the safety goals with their ASILs, or the assumed safety goals for an out-of-context element, are baselined.
Gate codes
The accelerator board, its power delivery and its cooling are designed and released, so bring-up boards are ready when silicon arrives.
Gate codes
Selects suppliers for their cybersecurity capability, agrees cybersecurity interface agreements with customers and suppliers, including chip and IP suppliers, flows requirements down, collects their evidence and keeps vulnerability and incident contacts working in both directions.
Discipline codes
A compound semiconductor used for high-voltage power devices, for example in electric vehicles.
Devices and interfaces
Used in: Power and compound lifecycle
The level that sets how much risk reduction an industrial or railway safety function must give.
Safety and security
Used in: IEC 61508 guide
Analyses signal and power integrity, heat and mechanical warpage across the dies, interposer and substrate together, from early estimates to sign-off.
Discipline codes
Production has shown the agreed stability, so the extra launch checks are removed with the customer's agreement and the part runs under the normal production control plan.
Gate codes
In: APQP lifecycle
Screens suppliers and in-house options, manages the supplier relationship and agreement, plans licence and compute capacity, tracks supplier change notices and closes licences at retirement.
Discipline codes
Agrees with each software, IP and hardware supplier what processes, work products and evidence they provide, monitors their progress and quality, takes in their deliveries and checks them, and includes their capability in the organisation's own.
Discipline codes
The certification body's first stage audit has confirmed the scope, documentation and readiness, and any areas of concern are addressed before the second stage.
Gate codes
In: QMS lifecycle
Assesses the supply continuity of the technology, package and materials, plans die and wafer banks, runs the obsolescence watch and the regular supply reviews, keeps counterfeit avoidance and traceability in place through authorised supply, and closes supply through the last-time buy and final lots.
Discipline codes
In: Space lifecycle
Plans the supply life, approves long-life components and second sources, watches components, processes and tools for obsolescence, and runs change notification, last-time buys and redesign decisions.
Discipline codes
A chip that brings processors, memory, interfaces and other functions together on one die.
Design and verification
Used in: SoC lifecycle, SoC lifecycle: SoC Specification & Architecture, SoC lifecycle: SoC RTL Design, SoC lifecycle: SoC architecture and specification, SoC lifecycle: SoC RTL design, AMS lifecycle: Tape-out or SoC Hand-off, and 2 more
In automotive work, the date series production of a vehicle or part begins.
Business and product lifecycleGate codes
Firmware, drivers, runtime and compiler run on silicon, the target workloads run end to end with correct results, and differences from the design are listed as errata.
Gate codes
Safety risks that come from a function working as designed but not being good enough for the situation.
Safety and securityStandards and regulations
Used in: ISO 21448 guide
The human review policy and accountability matrix are approved: who reviews AI-assisted outputs, with which checks, and which named engineer signs off each deliverable that includes them.
Gate codes
The platform software, firmware, SDK and build system are feature complete on the virtual platform, and a derivative configuration can be built from them.
Gate codes
Owns the decision to adopt, fund, continue or retire the step, the business case behind it and the approval of the data and IP position and the accountability matrix.
Discipline codes
Owns the reason for the program, funds it, removes blockers, accepts the scope and the outcome, and reviews whether capability holds once the assessment is over.
Discipline codes
The item or its out-of-context assumptions are defined, the customer and supplier have agreed who does which safety work, and the safety plan and the quality plan are approved.
Gate codes
Watching process measurements on control charts so drift is caught before it makes bad parts.
Quality and reliability
Used in: MSA and SPC guide
Sets the site requirements, runs the site search and evaluation, secures land, leads permitting with the authorities and community, negotiates the incentive agreements and reports against their conditions for the life of the fab.
Discipline codes
The process assessment approach behind Automotive SPICE; in circuit design the same letters name the simulator family.
Quality and reliability
Used in: Automotive SPICE guide, Automotive SPICE lifecycle, Traceability overlay
A versioned release package goes to SoC teams and licensees as silicon proven, with its silicon report, errata and a route for support.
Gate codes
A regular review of field issues, customer needs and cost decides the long-term support branches, the operating system and toolchain versions to carry forward and when final support begins.
Gate codes
The shrink or derivative is characterised and requalified, customers are notified of the change and those who need to have requalified it.
Gate codes
In: Memory lifecycle
Parts built on the production line, in the flight package and screened to the flight flow, start qualification to the agreed framework.
Gate codes
In: Space lifecycle
Brings the sub-tier suppliers into the plan: wafer foundry, assembly and test subcontractors, substrates, materials and services, with their own approvals, FMEAs and control plans, and the flow-down of customer specific requirements.
Discipline codes
In: APQP lifecycle
Approves and monitors suppliers, including foundries, assembly and test subcontractors and materials suppliers, flows customer requirements down, audits suppliers and develops those that need it.
Discipline codes
In: QMS lifecycle
The software stack has been reviewed against the threat model, the signing service and key management are in place, secure update is designed, and the vulnerability handling process is agreed.
Gate codes
A periodic review of test cost, test escapes, customer returns, hardware health and open changes, deciding what to improve, change or retire next.
Gate codes
The board reviews how the product and the company are scaling, and decides the next product, derivatives, second sources, the next round or strategic options.
Gate codes
A periodic review of yield, field returns, supplier changes and the certification position, with decisions on changes and their customer and regulatory notices.
Gate codes
In: RF lifecycle
The device software is built from controlled sources, verified to the depth its safety class requires, its software of unknown provenance is assessed, its bill of materials is generated and its security testing is done, and a release is recorded for design verification.
Gate codes
The firmware and software are complete for their integrity level, verified at unit and integration level, built from a controlled configuration with a software bill of materials, and released to system verification.
Gate codes
The software update management system is in place for the vehicle type, software versions that bear on type approval are identified, and the update path is secured and tested.
Gate codes
Fast memory built from logic transistors, used for caches and on-chip buffers.
Devices and interfaces
A site is chosen against the site requirements, with its energy, water, workforce, infrastructure, supply chain, sustainability and incentive position assessed and the land secured or under option.
Gate codes
The security support plan, certificates and regulatory reports are reviewed against the products still in the field.
Gate codes
Owns the allocated system requirements, the functional hazard assessment, the preliminary and final system safety assessments, the assurance level allocation and the safety review of derived requirements, design changes and in-service problems.
Discipline codes
Writes the low-level drivers and the safety software library that configure, test and report the chip's safety mechanisms, developed to the software parts of ISO 26262.
Discipline codes
The shrink or derivative die is designed and verified on the improved process and its tape-out database is released to mask making, which starts the shrink's own silicon, characterisation and requalification.
Gate codes
In: Memory lifecycle
Type testing for basic safety and essential performance to IEC 60601-1 and its applicable collateral and particular standards, and electromagnetic compatibility to IEC 60601-1-2, is complete, with test reports issued and any failures resolved and retested.
Gate codes
Designs and builds the package and, for HBM and stacked products, the stack: through-silicon vias, thinning, bonding, known good die and stack test, thermal and warpage control, and the stack handed to the package and chiplet teams who place it beside a processor.
Discipline codes
In: Memory lifecycle
Specifies, sources and qualifies the starting material: silicon carbide crystal growth and wafering, epitaxial layers with their doping and defect limits, gallium nitride epitaxy on its host substrate and silicon wafers for silicon devices, with supplier audits, incoming inspection, supply agreements, larger-diameter substrates and second sources.
Discipline codes
A vehicle maker's system for managing software updates safely, needed for type approval.
Safety and security
Used in: UN R156 guide, Vehicle cybersecurity lifecycle: SUMS ready gate
Onboards customers to each release, answers their questions, logs and tracks errata, and sends update releases and impact statements to the users they affect.
Discipline codes
In: PDK lifecycle
Plans and secures supply across photonic wafers, electronic wafers, lasers, fibres and assembly, sets up the ramp, and runs the last-time buy and the archive.
Discipline codes
The chip has been measured against its specification on the bench, with any differences listed as errata.
Gate codes
The macro has been measured against its specification across voltage, temperature and process corners, the views are correlated with silicon, and every difference is listed as errata.
Gate codes
The product meets its requirements in system testing and has passed the compliance tests its market requires.
Gate codes
Product silicon has been brought up on the evaluation board and checked against the silicon validation plan, with firmware running and the known issues written down, so the company knows what its samples can and cannot do before they ship.
Gate codes
Brings up first silicon, validates function and performance over temperature and voltage, characterises the parameters radiation will shift, and publishes the errata.
Discipline codes
In: Space lifecycle
Plans and runs the verification that proves the security requirements: formal security properties, negative and abuse case tests, fault injection simulation and firmware security tests, with traceability from every threat to the tests that cover it.
Discipline codes
Owns the software verification plan, reviews and analyses of requirements, design and code, requirements-based and robustness tests on the target, structural coverage analysis and the software verification results.
Discipline codes
Tests the whole product against its requirements, and runs electromagnetic compatibility, safety and other compliance tests.
Discipline codes
In: FPGA lifecycle
Verifies the design against its hardware safety requirements, runs fault injection campaigns to measure diagnostic coverage, and keeps every requirement traced to its evidence.
Discipline codes
Functional verification of the hardware design is closed against its plan, every hardware safety requirement is verified and the diagnostic coverage claimed in the FMEDA is confirmed by fault injection.
Gate codes
Writes the boot code, board support package, drivers and application software that run on the FPGA's processor or a processor beside it.
Discipline codes
In: FPGA lifecycle
Writes the prototype and test chip software and the evaluation software design partners run.
Discipline codes
Builds and maintains the software that runs the tool and connects it to the fab: sequencing, recipes, interlock logic, process control, alarms and the user interface, data collection, the factory host interface to the public SEMI standards, remote service access and equipment cybersecurity.
Discipline codes
Plans and develops firmware and device software under IEC 62304 for its safety class, from software requirements and architecture to unit, integration and system testing, software of unknown provenance, the software bill of materials, release and maintenance.
Discipline codes
Owns the software development plan and standards, the high-level and low-level requirements, the architecture, the source code and the executable object code, following DO-178C at the assigned level.
Discipline codes
Develops the embedded firmware, safety software, communication stacks and update mechanism to the integrity level and the secure development process, with qualified tools and a software bill of materials.
Discipline codes
Derives and analyses software requirements, designs the software architecture and detailed design, writes the units, and keeps them consistent and traceable to the system requirements and architecture.
Discipline codes
Specifies, builds and fixes the security software: secure boot stages, cryptographic services, secure onboard communication, diagnostics access control, intrusion detection sensors and logging, under secure coding rules.
Discipline codes
Builds the operating system, middleware and applications of the system, starting on models before hardware exists and continuing through validation, release and updates.
Discipline codes
In: System lifecycle
Builds the shared software base: operating system support, middleware and libraries, with the configuration options each derivative selects, and maintains it for every product on the platform.
Discipline codes
Builds the experimental flow used to explore the fabric, then adds the device to the vendor's design software: device model, synthesis and packing, placement, routing, timing analysis, power estimation and bitstream generation, with timing data that moves from advance to production.
Discipline codes
The production compiler, runtime and drivers are released from the qualified release candidate, built from tagged sources and signed, so the integrated software release can be published with the product.
Gate codes
Builds executable models of the chip, such as SystemC transaction-level models, to explore the architecture and to give software teams a virtual platform long before RTL is ready.
Discipline codes
In: SoC lifecycle
Designs the accelerator card or module, its power delivery from the rack to the die, and its air or liquid cooling, and builds the bring-up and production boards.
Discipline codes
Writes the sensing specification and the system error budget from the target applications, supports lead customers with evaluation kits, application notes and datasheets, and feeds field performance back.
Discipline codes
Turns the requirements into an architecture and a link budget, splits the system targets into block specifications, and keeps the budget honest as simulation and measurement results come in.
Discipline codes
In: RF lifecycle
Plans and runs validation of the link in the target system: evaluation platforms, bit error rate and margin, conformance to the named optical interface standards, interoperability testing with transceiver and host partners, laser safety classification, customer support and application notes.
Discipline codes
The last parts are tested and the program, patterns, hardware design data and test data are archived for the retention period, so a later question can still be answered.
Gate codes
The founders agree that the problem is real, stated by potential customers in their own words, large enough to build a company on and solvable with a chip they can make, and decide to form a company around it.
Gate codes
The business approves moving the device or platform to a larger substrate diameter, with a business case, a transition plan and the customer notification approach agreed.
Gate codes
An installed tool passes its site acceptance test and the customer's process acceptance, and the customer signs final acceptance, which starts warranty and service.
Gate codes
Threat analysis and risk assessment is complete for the item, every risk has a treatment decision, and later changes to the TARA go through review.
Gate codes
Identifies the assets, describes the attackers and their access, maps the attack surface, rates each risk and records how it is treated, writes the security requirements from the risks to mitigate, and keeps the threat model current as the design and public attacks change.
Discipline codes
The analysis of how a vehicle function could be attacked and how serious each risk is.
Safety and security
Used in: Vehicle cybersecurity lifecycle, Vehicle cybersecurity lifecycle: Threat Analysis & Risk Assessment (TARA), Vehicle cybersecurity lifecycle: TARA baselined gate
Places the node on the technology roadmap, owns its business case, cost and pricing, customer commitments and agreements, and decides when to refresh or withdraw it.
Discipline codes
Places the package technology on the roadmap, owns its business case, cost model and pricing, investment and volume terms, and decides when to refresh or withdraw it.
Discipline codes
The design meets every timing constraint on the chosen device and a bitstream is built from the frozen, signed-off source.
Gate codes
In: FPGA lifecycle
The product's test approach is accepted in outline: the quality level the market expects, the cost of test the business case can carry, and a test team named to work with design from the start.
Gate codes
The process technologies, wafer size, capacity, product mix and phasing the fab is planned around are chosen, with a first tool list and wafer cost estimate.
Gate codes
Classifies the tool, its spares, upgrades, software and technical data under the export control rules of every country involved, screens customers, end uses and end users, obtains and tracks licences, controls technology shared with partners and remote service access, and keeps the records the rules require.
Discipline codes
Simulation of how a process step or a device behaves physically, used to develop processes and devices.
Design and verification
Used in: Power and compound lifecycle: Device design and TCAD
Chooses the process technologies, wafer size, capacity and product mix, turns the process flow into a tool list with counts and facility needs, and keeps the wafer cost model current as the plan changes.
Discipline codes
The frozen test chip is signed off for the shuttle: verification against its plan, timing, power, physical verification and the foundry's checks are clean or waived, and the RTL has run on the prototype platform, so the database can be released.
Gate codes
The test chip carrying the macro, its test structures and its measurement interface is checked and its database released to the foundry; this version of the macro is locked.
Gate codes
Plans and designs the test vehicles, measures their device, defect and memory structures on wafer, and supplies the parametric data that models, yield and qualification depend on.
Discipline codes
The node's targets, device menu, design rule intent, cost and business case are agreed, and the investment to develop it is committed.
Gate codes
One or more prospective founders write down the idea for a chip in a few sentences, with the problem it solves and the advantage it claims, and agree to spend time testing it with potential customers, technical experts and public data, including the evidence that would make them stop.
Gate codes
Defines the datalog content and formats, runs the test data pipeline and dashboards, and develops outlier screening and adaptive test rules from the data.
Discipline codes
The tile circuits and the device RTL are feature complete.
Gate codes
Compares the candidate technologies, works with the foundry on the design kit version and device models, validates models at the frequencies and powers the product uses, and correlates them with silicon.
Discipline codes
In: RF lifecycle
Owns the test strategy, test patterns and the test programs used for validation, screening at temperature, burn-in and lot acceptance, with the burn-in and test hardware.
Discipline codes
In: Space lifecycle
Develops the production test program with the screening automotive customers expect, such as outlier screening and tests at more than one temperature, and runs yield and test data analysis in production.
Discipline codes
Plans how the test chip is packaged and tested through outsourced assembly and test suppliers, and delivers packaged test chips for evaluation.
Discipline codes
Before the specification is frozen and development is committed, the team shows that the process, critical IP, package and thermal technology can meet the targets, or records each gap and how it will close.
Gate codes
In: SoC lifecycle, Soft IP lifecycle, Hard IP lifecycle, AI accelerator lifecycle, Medical lifecycle, Avionics lifecycle, Industrial lifecycle, System lifecycle, Platform lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
For a vehicle maker, the vehicle type is approved for cybersecurity under UN R155; for a supplier, the evidence its customer needed for approval has been delivered and accepted.
Gate codes
Designs the repeating logic, routing and memory tiles and their configuration cells, largely as custom circuits and layout, and assembles the fabric from them.
Discipline codes
Writes installation specifications, moves tools in, connects, starts up and accepts them with their suppliers, qualifies them on wafers, then raises and holds equipment availability, and removes or transfers tools at the end.
Discipline codes
Plans electrical test of the test vehicles, including die-to-die interface tests against UCIe where it is used, defines incoming die and known good die requirements with die suppliers, builds the test flow for stacked and multi-die packages and releases production test.
Discipline codes
Provides the toolchains, SDK, build and continuous integration system that let every derivative team configure, build and test its software from the shared base.
Discipline codes
The attackers in scope, the attack surface and the risk to each asset are analysed and reviewed, and every high risk has a treatment decision.
Gate codes
Owns the system: sets the quality policy and objectives, makes the system part of the business, provides resources, holds the management reviews and is accountable for the certificate and for customer satisfaction.
Discipline codes
In: QMS lifecycle
The chip database, or each die of a multi-die product, is signed off and handed to the foundry for masks and wafers.
Gate codes
In: Product lifecycle, SoC lifecycle, Automotive lifecycle, AI accelerator lifecycle, Memory lifecycle, Space lifecycle, Photonics lifecycle, RF lifecycle, FPGA chip lifecycle
The signed-off block is released to the SoC team with its views and models, or taped out as a stand-alone chip or test chip.
Gate codes
In: AMS lifecycle
Custom chips are signed off and released for manufacture, and the board designs are released under design control, with chip-level risk controls verified, the hardware design description complete and the design review held.
Gate codes
The masks for the custom layers are released to manufacture and accepted, and banked base wafers are allocated to the customer device.
Gate codes
The test plan, the insertion split and the cost and capacity it needs are approved, so the product's unit cost and supply plans include a realistic cost of test.
Gate codes
The production test and calibration programs, limits and hardware are released, based on characterisation across temperature, supply and stimulus.
Gate codes
Writes, debugs, optimises, releases and maintains the test program: flow, test methods, levels, timing, limits, bins and datalogs for every insertion.
Discipline codes
Owns the test strategy, the cost of test and the test capacity plan, and runs the test releases and their reviews with product management and operations.
Discipline codes
The test program loads, runs end to end and bins correctly on the tester with its hardware before silicon arrives, so first silicon tests the chip rather than the program.
Gate codes
The process meets its intrinsic reliability targets on qualification vehicles built on the frozen baseline, and the technology qualification report is approved.
Gate codes
The locked tool, model and settings meet the success criteria on the full reference design set, their failure modes are catalogued with the check that catches each one, and the scope the qualification covers is stated.
Gate codes
The tools needed for the first full-flow lots have passed acceptance, safety sign-off and wafer qualification, and are connected to factory automation.
Gate codes
Test vehicles built on the frozen baseline pass the component-level and board-level reliability tests in the plan, every failure has been analysed, and the technology qualification report is approved.
Gate codes
Sets what the test must screen for each market, reviews coverage and screening before release, and owns excursions, test escapes and customer returns with their corrective actions.
Discipline codes
Builds the reference design set and success criteria, measures accuracy, repeatability and failure modes against known answers, and reruns the references on a schedule and after every change.
Discipline codes
Owns the assessment of every design and verification tool, the qualification of tools whose output is not otherwise verified, using DO-330 for software tools, and control of the design environment so builds can be reproduced.
Discipline codes
The transducer layout is checked against the MEMS design rules and the multiphysics model, and the MEMS mask set is released for prototype wafers.
Gate codes
A periodic review decides whether to extend the technology with new options, reduce its cost, move it to new sites, or plan its successor and withdrawal.
Gate codes
Representative units built on the production process, with a reviewed type test plan agreed with the test laboratories and certification bodies, are ready for validation and type testing.
Gate codes
Everything needed for a significant production run at the planned rate is ready: production tooling and equipment, released test programs and fixtures, trained operators, production materials from approved suppliers and the pre-launch control plan in use.
Gate codes
In: APQP lifecycle
A gate that checks the technology is ready before the next commitment.
Gate codes
Used in: SoC lifecycle: Technology feasibility, SoC lifecycle: Tape-out technology readiness, SoC lifecycle: Qualification passed, Soft IP lifecycle: Technology feasibility, Soft IP lifecycle: IP verification sign-off, Hard IP lifecycle: Technology feasibility, and 71 more
Identifies assets and damage scenarios, describes threat scenarios and attack paths, rates impact and attack feasibility, determines risk and records treatment decisions, and keeps the TARA current as the design and the threat landscape change.
Discipline codes
Checks that the technology and the concept are feasible before the commitment to develop.
Gate codes
Used in: SoC lifecycle: Technology feasibility, Soft IP lifecycle: Technology feasibility, Hard IP lifecycle: Technology feasibility, AMS lifecycle: Process and device readiness, Chiplet lifecycle: Partitioning freeze, Automotive lifecycle: Automotive technology readiness, and 20 more
Checks that the design or the technology is ready before a freeze or a tape-out.
Gate codes
Used in: SoC lifecycle: Tape-out technology readiness, Soft IP lifecycle: IP verification sign-off, Hard IP lifecycle: Hard macro sign-off, AMS lifecycle: Post-layout sign-off, Chiplet lifecycle: Multi-die sign-off, Automotive lifecycle: Tape-out, and 20 more
Checks that the technology is ready for production before release.
Gate codes
Used in: SoC lifecycle: Qualification passed, Hard IP lifecycle: Reliability qualified, AMS lifecycle: Qualification passed, Chiplet lifecycle: Package qualification passed, Automotive lifecycle: AEC-Q100 qualified, AI accelerator lifecycle: Qualification passed, and 19 more
Chooses the transduction principle and designs the mechanical structure, its electrodes, springs, proof mass, membrane or resonator, and lays it out to the MEMS design rules, then corrects it from prototype results.
Discipline codes
The test chip RTL is complete for the scope the test chip must prove, with its IP integrated and most of the verification plan run; from here only reviewed fixes go in, so the sign-off can close on a stable design.
Gate codes
Writes training on how to use the step, its limits and the review it requires, trains users before they get access, keeps training records and helps teams through the change in how the work is done.
Discipline codes
The list of tests, their conditions and their draft limits is baselined, with every datasheet parameter and fault model traced to a test or to a stated reason why it is not tested.
Gate codes
The semiconductor technology for each die is chosen, the process design kit version is identified and the device models are judged good enough for design, or the gaps are covered by test structures; the architecture and link budget are then frozen on the chosen technology.
Gate codes
In: RF lifecycle
The US law under which chemical substances, including PFAS, are reported and regulated.
Export, trade and product law
Writes the test plan and the test specification, keeps the coverage matrix that traces every datasheet parameter and fault model to a test, and defines the test flow and bins.
Discipline codes
The tool list for first-phase capacity is final and the remaining purchase orders are released, with delivery and move-in sequence agreed against the cleanroom schedule.
Gate codes
Tests every wafer and part: wafer-level parametric and blocking tests, high-current and high-voltage final test, dynamic tests where needed, screening such as gate stress or burn-in where the plan requires it, outlier detection and the test data that yield and quality teams rely on.
Discipline codes
Probes the MEMS and ASIC wafers, measures prototypes, characterises the sensor across temperature, supply and stimulus, and builds the production test program, limits and test capacity.
Discipline codes
Plans how every part is tested, mostly by loading test configurations that exercise the fabric, routing and memories, with scan and built-in self-test for the hard IP, and releases the binning and production test programs.
Discipline codes
Builds the test architecture into the base array and its fixed layers, and proves it on base wafers and the validation vehicles, so every customer design's test is built on it.
Discipline codes
A vertical connection through a silicon die, used to stack dies and in interposers.
Manufacturing, test and packaging
Used in: Package technology lifecycle: Interposer, TSV and hybrid bonding
Test time and cost per good part meet the target in the cost model, with every reduction justified by data and reviewed for its quality risk.
Gate codes
The signed-off test chip database has been released and accepted for the booked shuttle or run, with the board, package and lab plan ready for when silicon returns.
Gate codes
Plans and runs the type tests with accredited laboratories: EMC emissions and immunity, electrical safety, environmental and mechanical tests, and explosion protection tests where the product is for hazardous areas.
Discipline codes
Before the database is released, the team confirms that the technology the design depends on is ready: the process design kit used for sign-off, the silicon status of the IP, and the package, test and reliability technology needed for first silicon.
Gate codes
In: SoC lifecycle
The test chip has been brought up and measured, its results compared with the model, and the founders know which claims held on silicon, which did not, and what product silicon must change.
Gate codes
Plans and runs software testing from models to silicon: unit and integration tests, regression on virtual platforms and emulation, hardware-in-the-loop rigs, stress, performance, power, update and compliance testing.
Discipline codes
Designs the test vehicles, daisy chains, Kelvin structures, thermal test dies and monitor structures that prove each module and the full flow, and measures them as they come off the line.
Discipline codes
The test vehicle designs, with their daisy chains, monitor structures and dummy or functional dies, are checked against the preliminary rules and released for wafer, substrate and mask build.
Gate codes
Prepares and maintains the regulatory evidence: CSMS and SUMS certificates of compliance, the vehicle type approval documentation for UN R155 and UN R156, contact with the approval authority and technical service, and reporting of monitoring results.
Discipline codes
Tests test vehicles and product wafers, builds the wafer and package test flows with redundancy analysis and repair, reads fail bit maps back to process and design causes, and raises yield and good bits per wafer.
Discipline codes
In: Memory lifecycle
A specific flow step, its current cost and the value of assisting it are described, the consequence of a wrong output there is understood, and an owner is funded to plan an evaluation.
Gate codes
Update campaigns are reviewed: each was assessed for its effect on safety, cybersecurity and type approval, delivered safely and recorded, and the lessons are applied.
Gate codes
An open standard for die-to-die links between chiplets in one package.
Devices and interfaces
Used in: Chiplet lifecycle, Interoperability and compliance overlay
Runs usability engineering to IEC 62366-1, from the use specification and use-related risk analysis through formative evaluations to the summative evaluation, and leads design validation, labelling and instructions for use.
Discipline codes
The product marking used in Great Britain in place of CE marking for many goods.
Export, trade and product law
A UN regulation under the UNECE agreement on vehicle type approval.
Standards and regulations
Used in: UN R155 guide
The companion regulation to UN R155 for software updates.
Standards and regulations
Used in: UN R156 guide
A sponsor asks for candidate flow steps to be examined for AI assistance, says why now, and gives a small team the time to compare the candidates, measure how the step is done today and classify its data, before any tool is screened or any design data is used.
Gate codes
Builds, signs and releases security updates, keeps the software bill of materials current, manages key revocation and anti-rollback, and issues the final security update.
Discipline codes
Designs the secure update path and runs the software update management system: software identification, update impact assessment, package signing and verification, campaign delivery and records.
Discipline codes
An update release fixes errata or follows a process change, with release notes that say what changed, which designs are affected and whether existing tape-outs need any action.
Gate codes
In: PDK lifecycle
A security update is built, signed, tested and released, with rollback protection and customer notice.
Gate codes
An upgrade kit, field change or software update is released with its validation, its export classification and the customer notices it needs.
Gate codes
A software and firmware update is validated on the shipped configurations and released to the field, with release notes and any security advisories.
Gate codes
In: System lifecycle
The Universal Serial Bus specifications, with the USB Implementers Forum running compliance testing, certification and the logo programme.
Standards and regulations
Used in: Interoperability and compliance overlay, USB-IF compliance guide
The current USB specification, unifying USB data, DisplayPort video and Thunderbolt-style PCIe tunneling over one reversible Type-C connector.
Standards and regulations
Used in: USB4 in the standards register
Every software unit in the release is designed, implemented and verified against its criteria, with results recorded and traced.
Gate codes
A widely used method and class library for building testbenches that verify digital designs.
Design and verification
Validates the cybersecurity goals and claims on the item in its environment, runs penetration tests against the attack paths in the TARA, and assembles the cybersecurity case.
Discipline codes
Brings up the first silicon in the lab and checks it against the specification.
Discipline codes
In: SoC lifecycle
Brings up first silicon, characterises it across temperature and supply corners, and tests every safety mechanism on silicon.
Discipline codes
Designs the lab and test boards, brings up the test chip, measures it against the model, writes the lessons for product silicon and builds the evaluation kits design partners use.
Discipline codes
Every design input has a passing verification result traced to it, every risk control is verified as implemented and effective, and a design review accepts the verification evidence.
Gate codes
Requirements-based verification is complete on the target, structural coverage and the advanced hardware verification methods are complete or justified, open problem reports are assessed, and the system safety assessment is closed for this baseline.
Gate codes
The FMEDA, dependent failure analysis, fault insertion, hardware and software verification and security verification are complete, and the product meets its integrity and security targets on analysis and test.
Gate codes
Validation shows that the cybersecurity goals are achieved and the claims hold for the item in its operational environment.
Gate codes
The German automotive industry association, publisher of Automotive SPICE and quality handbooks.
Standards bodies and agencies
Used in: AIAG and VDA FMEA guide
Verifies that the implemented item meets its cybersecurity requirements: requirement-based tests, interface and fuzz testing, vulnerability scanning and the analysis of weaknesses introduced during development.
Discipline codes
Verifies the ASIC and the transducer together, with behavioural models of the transducer in mixed-signal simulation across corners, mismatch and stimulus, and compares the system model with prototype results.
Discipline codes
Plans and runs verification of the RF and mixed-signal design: block and top-level simulation with modulated signals, the digital control and calibration paths, and regression of post-layout results.
Discipline codes
In: RF lifecycle
Plans and runs functional verification and fault injection, so that every protected function is shown to correct, detect or tolerate the upsets the mitigation architecture lists.
Discipline codes
In: Space lifecycle
The other major hardware description language, especially entrenched in defense, aerospace and European design flows, valued for its strict typing catching more design errors at compile time than Verilog's looser syntax.
Standards and regulations
Design validation on production-equivalent units and the summative usability evaluation show the device meets user needs and intended use, residual risk is judged acceptable against benefit, and the risk management report is approved.
Gate codes
Every safety function is validated, and the EMC, electrical safety, environmental, explosion protection and interoperability tests are passed, with the reports needed for certification.
Gate codes
Review pilot outputs independently, define the independent check that catches each failure mode, update verification sign-off criteria and review errors found during first use.
Discipline codes
Proves the system meets its requirements: the validation plan, functional, performance, power, thermal, reliability and software testing on the design and production validation builds, and pre-compliance checks.
Discipline codes
In: System lifecycle
A virtual prototype of the system is released to the software and firmware teams, with its scope, fidelity and known gaps stated, so software development can start before hardware exists.
Gate codes
In: System lifecycle
The virtual platform is released to the software, firmware and derivative teams with its fidelity and limits stated, so software development and derivative studies can start before silicon.
Gate codes
Builds and runs the pre-silicon targets the software is developed on: fast instruction-accurate virtual platforms, emulation and FPGA prototypes of the RTL, and the hybrid set-ups that join them, then correlates them with silicon.
Discipline codes
Builds executable models of the system before its hardware exists, so software can start early and architecture choices can be checked against real workloads.
Discipline codes
In: System lifecycle
Builds and maintains the virtual platform and the performance and power models that every derivative shares, so software starts before silicon and each derivative can be studied before it is committed.
Discipline codes
Output scales up towards forecast demand as design wins move into production, with yield, delivery and early field quality watched closely.
Gate codes
In: Product lifecycle, SoC lifecycle, Photonics lifecycle, Power and compound lifecycle, MEMS and sensors lifecycle, RF lifecycle, System lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
Test capacity, hardware sets, operators and data monitoring are ready for volume, so the ramp is not limited by test.
Gate codes
Units built to the released design, characterised chips, released software and approved test plans are available, so design verification and type testing at the laboratory can start on a known configuration.
Gate codes
Vulnerabilities found in the field are reviewed: each has been analysed against the TARA and managed, and monitoring results are reported where required.
Gate codes
Receives and triages vulnerability reports, coordinates fixes and disclosure, runs the update delivery service, and watches the third-party and open-source components in the software bill of materials.
Discipline codes
Coverage goals in the verification plan are met, and every open bug is fixed or waived with a recorded reason.
Gate codes
In: SoC lifecycle, FPGA lifecycle, AI accelerator lifecycle, FPGA chip lifecycle
The release candidate has passed validation on silicon across the supported boards, configurations and operating systems, compliance testing is complete and the quality record is ready.
Gate codes
The die design is verified against its specification and the chosen interface standard across corners, with repair, test modes and error correction checked.
Gate codes
In: Memory lifecycle
Every security requirement is verified or has an accepted residual risk, security properties are proven or covered, fault and leakage assessments are reviewed, and the design is ready for tape-out from a security point of view.
Gate codes
Plans and runs verification and validation: hardware and software verification against the traceability matrix, fault insertion of the diagnostics, safety validation of each safety function, and interoperability and conformance testing.
Discipline codes
The first base wafers have been processed up to the first customisable layer, have passed wafer acceptance checks and are held in the wafer bank.
Gate codes
The guidelines for making web content usable by people with disabilities.
Export, trade and product lawStandards and regulations
Devices built on the larger wafer match those on the original wafer within agreed limits, from substrate and epitaxy quality through parametrics to reliability, so qualification can be read across or repeated as planned.
Gate codes
The EU law on collecting and recycling electronic waste.
Export, trade and product law
Used in: RoHS, REACH and WEEE guide, Interoperability and compliance overlay
Assesses the workforce a site can supply, plans hiring, training and certification ahead of each phase, works with universities, colleges and public programmes on the skills pipeline, and reviews workforce health in operation.
Discipline codes
Chooses and characterises the models and workloads the accelerator is designed for, chooses data types with the numerics experts, and keeps the workload set current as models change.
Discipline codes
Packaging steps done on the whole wafer before it is cut into dies.
Manufacturing, test and packaging
Develops the wafer-level modules: under-bump metallurgy, solder bumps and copper pillars, redistribution layer lithography, plating and dielectrics, fan-out reconstitution and moulding, and panel-level variants where used.
Discipline codes
Lead customers' workloads run correctly, at the agreed accuracy and performance, on the release candidate software and the production system.
Gate codes
The models and workloads the design is judged against are chosen, characterised and agreed by product, architecture and software leads.
Gate codes
Yield and bin distributions are stable enough to set statistical bin limits and alarms, with the main yield detractors known and owned.
Gate codes
Finds and removes the causes of yield loss, sets the inline inspection and metrology plan, and holds the process in statistical control with fast excursion response.
Discipline codes
Test vehicles show defect density, memory yield and parametric spread on a trend to the targets set for customer products, with the main loss mechanisms understood.
Gate codes
Gate and discipline codes are plain initials chosen for the Hub's charts, not any company's internal codes. Standard names belong to their publishers; the guides explain them in our own words. Missing an abbreviation? Suggest one.