ATPG (Automatic Test Pattern Generation)

Notes

Classic algorithms are D-algorithm, PODEM and FAN; modern engines combine them with SAT solvers and heavy fault simulation.

Overview

Automatic test pattern generation (ATPG) is the software process that works out which input patterns to apply to a chip so that a tester can tell a good part from one with a manufacturing defect. It targets a list of modelled faults and produces the patterns, usually delivered through scan chains, together with a report of how many of those faults the patterns detect.

How it works

ATPG starts from the gate-level netlist and a fault model. The simplest, stuck-at, assumes a node is permanently tied to 0 or 1; transition or at-speed fault models assume a node switches too slowly, which catches timing-related defects. For each fault the tool must find inputs that both activate the fault (drive the node to the opposite value) and propagate its effect to a point the tester can observe.

Scan design makes this tractable. During test, the chip's flip-flops are linked into shift registers, so the tool can load any state directly and read the result out, turning a sequential problem into a much easier combinational one. Fault simulation then checks which other faults each pattern also detects, so the final set stays compact. Compression logic on the chip lets many internal scan chains share a few tester pins, cutting test data and test time.

The output is a set of patterns in a tester format and a coverage report. Test engineers translate the patterns into the test program, and failing patterns from production can later be fed back into diagnosis tools to locate defects.

Examples

• Generating stuck-at and transition patterns for a large SoC and reporting coverage for each fault model.
• Using on-chip scan compression so that hundreds of internal chains are driven from a handful of tester channels.
• Adding cell-aware fault models that target defects inside standard cells, often asked for in automotive parts.
• Running scan diagnosis on failing production dies to point failure analysis at a specific net.

Why it matters

Fault coverage from ATPG is a main measure of test quality, and pattern count drives test time and therefore cost. DFT and ATPG engineers own it, test engineers run the patterns, and yield and failure analysis teams use scan diagnosis to find what is killing dies. Automotive customers often demand very high coverage to meet defect-per-million targets.

In the chip lifecycle ATPG runs late in design, after scan insertion and synthesis, is refined through signoff, and its patterns are used at wafer sort and final test for the life of the product.

Related terms

• Scan chain
• Fault coverage
• Stuck-at fault
• Fault simulation

Where it appears on the Hub

Used on 49 pages of the Hub. In each group, the pages that mention it most come first.