ESD (Electrostatic Discharge)

Notes

ESD ratings have been falling as nodes shrink, so 500 V HBM and 250 V CDM are now accepted targets where 2 kV was once routine.

Overview

ESD (electrostatic discharge) is the sudden flow of static charge between objects at different voltages, such as a person, a tool or a chip, producing a current pulse lasting nanoseconds to microseconds that can destroy a chip's thin gate insulators, junctions or metal. Chips are protected in two ways: on-chip protection circuits on every pin, and controlled handling in factories, which together keep ESD damage rare.

How it works

Static charge builds up when materials touch and separate. When a charged person or object touches a chip pin, or a charged chip touches a grounded surface, the charge rushes through the device. Without protection, a discharge too small for a person to notice can break down a gate oxide only a few nanometres thick.

On-chip protection gives this current a safe path. Each input, output and supply pin connects to clamp circuits, such as diodes and large transistors, that turn on quickly during a discharge and shunt the current to the supply rails, with power clamps between rails. Designers must make these clamps strong enough to survive the pulse but invisible during normal operation, which is hard on high-speed and radio frequency pins where added capacitance hurts performance.

Chips are tested against standard models of how discharges happen. The human body model simulates a charged person touching a pin and is defined in the joint ESD Association and JEDEC standard JS-001. The charged device model simulates a chip that becomes charged and discharges to a grounded surface, the main risk in automated handling. Results classify each part by the voltage it withstands. Factories run ESD control programmes with grounded workstations, wrist straps, ionisers and protective packaging so that parts are not exposed to discharges beyond their rating.

Examples

• An I/O cell with diodes to each supply rail and a clamp between rails, used on every pin.
• A qualification report giving a part's human body model and charged device model ratings.
• A failure analysis finding a melted junction at one pin, traced to a handling step without proper grounding.
• A radio frequency pin with a low-capacitance protection design to preserve performance.
• An assembly line using ionisers and grounded trays to keep charged device model events below the parts' rating.

Why it matters

ESD failures appear in assembly, board manufacturing and the field, and can be hard to trace, so ESD and latch-up engineers, I/O cell designers and reliability engineers treat robustness as a design requirement. Customers set minimum ESD ratings, particularly in automotive markets.

In the chip lifecycle, ESD protection is designed into I/O libraries and checked in physical verification, ESD ratings are measured during qualification, and handling controls apply from wafer fab to board assembly.

It matters most to: ESD and I/O Cell Designer, ESD and Latch-Up Engineer, ESD and Latch-up Physical Verification Engineer, ESD and Latch-Up Qualification Engineer, Reliability Qualification Engineer

Common confusions

Not the same as EOS

Electrical overstress is damage from voltage or current beyond ratings for longer periods, for example from a faulty power supply. ESD is a very short, high-current event. Failure analysis tries to tell them apart. ESD vs EOS

Not the same as latch-up

Latch-up is a high-current state triggered when parasitic structures in CMOS switch on. It is tested separately, although ESD and latch-up are often handled by the same engineers.

Not the same as system-level ESD

System-level tests apply discharges to a finished product, such as a phone. Device-level tests such as the human body model apply them to an individual chip.

Related standards

• ANSI/ESDA/JEDEC JS-001 (ESD sensitivity testing, human body model, device level)

Sources

1. ANSI/ESDA/JEDEC JS-001-2024 (opens in a new tab), EOS/ESD Association, 2026-10-22
2. JS-001: Joint JEDEC/ESDA Standard for Electrostatic Discharge Sensitivity Test, Human Body Model (HBM), Device Level (opens in a new tab), JEDEC, 2026-10-22
3. EOS/ESD Association (opens in a new tab), EOS/ESD Association, 2026-10-22
4. Electrostatic discharge (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• Human Body Model
• Charged Device Model
• EOS
• Latch-up

Where it appears on the Hub

Used on 84 pages of the Hub. In each group, the pages that mention it most come first.