Chip lifecycle / Soft IP lifecycle / RTL to Early Access

RTL to Early Access

Writing the block's synthesisable design code until the main features are in and an early drop can go to SoC teams for integration trials and floorplanning, with its limits stated.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^A02 Micro-architecture

^AO03 RTL to Early AccessYou are here

^A04 RTL Completion

IP product milestones

IP engineering milestones

TFTR1TR1: Technology feasibility ISFIP specification freeze IMRMicro-architecture review EAEarly access release IRFIP RTL freeze

IP system modelling^A

0.3

0.5

0.8

IP performance analysis^A

0.3^D

0.5^D

IP RTL design^DOO

0.3^A

0.5^A

0.8^A

IP verification^DOO

0.3^A

0.5^D

0.8^A

IP FPGA prototyping^A

0.3

IP implementation views^DO

0.0

0.3

0.5

Third-party IP intake^DO

0.3

0.5^D

IP quality and release^DD

0.0

0.3

0.5

IP product management^AAO

0.3

0.5

0.8

Key0.0Specified0.3Pre-alpha0.5Alpha0.8Beta1.0ReleasedLockedFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.You are here: RTL to Early AccessAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

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Stages

IP product milestones

IP engineering milestones

TR1: Technology feasibility (TF) (technical readiness review TR1)
IP specification freeze (ISF)
Micro-architecture review (IMR)
Early access release (EA)
IP RTL freeze (IRF)

Disciplines

IP architecture^AO
- Micro-architecture: maturity 0.3, Pre-alpha. Specification clarified against the micro-architecture, with open questions tracked.
- RTL to Early Access: maturity 0.5, Alpha. Specification stable while the main features are coded; changes go through change control.
- RTL Completion: maturity 0.8, Beta. Specification matches the feature-complete RTL; only clarifications remain.
IP system modelling^A

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