Chip lifecycle / SoC lifecycle / Disciplines / Full-chip design for test

Full-chip design for test (DFT)

Adds and connects the full-chip test structures, such as scan chains and built-in self-test, around each IP block's own, so every manufactured chip can be tested.

Active in these stages

SoC Specification & Architecture
IP Integration
SoC RTL Design
Full-Chip Verification
Full-Chip DFT
Physical Design & Sign-off
Tape-out
Foundry & Mask
Packaging & Test
Bring-up & Silicon Validation
Qualification & Reliability
Production Ramp & Yield
Volume Production & Sustaining

Roles

DFT Architect →
DFT Implementation Engineer →
DFT Verification Engineer →

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