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The security practices that run on top of every lifecycle: a secure development lifecycle, threat modelling, hardware security architecture, security verification, supply chain integrity, vulnerability response and security updates.
Mapped onto 36 of 36 lifecycles: 432 of 432 stages and 683 of 683 gates have practices from this overlay.
Where security practices apply, lifecycle by stage
Each row is a lifecycle and each cell one of its stages, in order. A cell counts the practices whose phase matches the stage. Select a cell to open the stage, where the practices and the gate questions are listed.
1. Opportunity & Market Sensing: Security policy, ownership and a secure development lifecycle; Supply chain integrity: provenance and counterfeit prevention
2. Concept & Business Case: Security policy, ownership and a secure development lifecycle; Asset identification and threat modelling; Security requirements and assurance targets; Supply chain integrity: provenance and counterfeit prevention
3. Definition & Planning: Asset identification and threat modelling; Security requirements and assurance targets; Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states
4. Development: Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Security verification and penetration testing; Supply chain integrity: provenance and counterfeit prevention; Key provisioning and secure manufacturing
1. Concept & Feasibility: Security policy, ownership and a secure development lifecycle; Asset identification and threat modelling; Security requirements and assurance targets; Supply chain integrity: provenance and counterfeit prevention
2. SoC Specification & Architecture: Asset identification and threat modelling; Security requirements and assurance targets; Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states
3. IP Integration: Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Supply chain integrity: provenance and counterfeit prevention
4. SoC RTL Design: Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Supply chain integrity: provenance and counterfeit prevention
5. Full-Chip Verification: Side-channel and fault attack resistance; Security verification and penetration testing
6. Full-Chip DFT: Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Security verification and penetration testing; Supply chain integrity: provenance and counterfeit prevention
7. Physical Design & Sign-off: Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Security verification and penetration testing; Supply chain integrity: provenance and counterfeit prevention
8. Tape-out: Supply chain integrity: provenance and counterfeit prevention; Key provisioning and secure manufacturing
9. Foundry & Mask: Supply chain integrity: provenance and counterfeit prevention; Key provisioning and secure manufacturing
10. Packaging & Test: Side-channel and fault attack resistance; Security verification and penetration testing
13. Production Ramp & Yield: Secure debug, test access and device lifecycle states; Supply chain integrity: provenance and counterfeit prevention; Key provisioning and secure manufacturing; Vulnerability reporting, disclosure and response
14. Volume Production & Sustaining: Secure debug, test access and device lifecycle states; Supply chain integrity: provenance and counterfeit prevention; Key provisioning and secure manufacturing; Vulnerability reporting, disclosure and response; Security updates, revocation and end of support
15. End of Life: Security updates, revocation and end of support
1. IP Specification & Architecture: Security policy, ownership and a secure development lifecycle; Asset identification and threat modelling; Security requirements and assurance targets; Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Supply chain integrity: provenance and counterfeit prevention
2. Micro-architecture: Asset identification and threat modelling; Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Supply chain integrity: provenance and counterfeit prevention
3. RTL to Early Access: Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Supply chain integrity: provenance and counterfeit prevention
4. RTL Completion: Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Security verification and penetration testing; Supply chain integrity: provenance and counterfeit prevention
5. IP Verification: Side-channel and fault attack resistance; Security verification and penetration testing
6. IP DFT & Implementation Views: Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Security verification and penetration testing; Supply chain integrity: provenance and counterfeit prevention
7. IP Quality Checks: Side-channel and fault attack resistance; Security verification and penetration testing; Security evaluation and certification evidence
8. IP Release & Hand-off: Supply chain integrity: provenance and counterfeit prevention; Key provisioning and secure manufacturing; Vulnerability reporting, disclosure and response; Security updates, revocation and end of support
1. Specification & Process Selection: Security policy, ownership and a secure development lifecycle; Asset identification and threat modelling; Security requirements and assurance targets; Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Supply chain integrity: provenance and counterfeit prevention
2. Circuit & Block Design: Asset identification and threat modelling; Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Supply chain integrity: provenance and counterfeit prevention
3. Design Verification & Early Views: Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Security verification and penetration testing; Supply chain integrity: provenance and counterfeit prevention
4. Physical Implementation: Hardware security architecture: roots of trust, key storage and isolation; Secure debug, test access and device lifecycle states; Side-channel and fault attack resistance; Supply chain integrity: provenance and counterfeit prevention
5. Physical Sign-off & Characterisation: Side-channel and fault attack resistance; Security verification and penetration testing; Supply chain integrity: provenance and counterfeit prevention; Key provisioning and secure manufacturing
6. Test Chip Tape-out: Supply chain integrity: provenance and counterfeit prevention; Key provisioning and secure manufacturing
7. Silicon Validation & Reliability: Side-channel and fault attack resistance; Security verification and penetration testing; Security evaluation and certification evidence
8. Quality Checks & Release: Supply chain integrity: provenance and counterfeit prevention; Key provisioning and secure manufacturing; Security evaluation and certification evidence
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.