Acronym · General Industry
MPW (Multi-Project Wafer)
A shared mask set and wafer run carrying designs from several unrelated customers, splitting mask and wafer costs between them. It is how universities, startups and prototype projects obtain real silicon at an affordable price.
- Also known as
- Shuttle run, Multi-project chip
- Type
- Acronym
- Domain
- General Industry, Design and product flow
Notes
Europractice, MOSIS, CMP and the foundries' own shuttle programmes are the main routes to MPW access.
Overview
An MPW, or multi-project wafer, is a fabrication arrangement in which designs from several different customers are combined on one mask set and processed on the same wafers, so that each pays only a share of the mask and wafer cost. It makes prototypes, test chips and research designs affordable on processes where a full mask set would cost far more than the project could justify. Scheduled MPW runs offered by foundries and brokers are usually called shuttles.
How it works
The organiser collects finished layouts from each participant, checks them and combines them onto one shared mask set. The foundry then processes the wafers in the normal way. Afterwards the wafers are diced and each participant receives dies cut from its own part of the layout, usually unpackaged and untested. Because the masks and wafers are shared, the cost is divided by area: Europractice prices most runs per square millimetre with a minimum charge, so a small design pays a fraction of what a dedicated mask set would cost.
The savings are what make the model work. TSMC says its CyberShuttle service, which offers up to ten shuttles a month on processes from 0.5 micron to A14, can cut prototyping cost by up to 90 per cent and significantly reduces NRE. Europractice names MPW runs and multi-layer mask (MLM) runs as the two techniques it uses to lower prototyping cost. Shared runs are not new: the US MOSIS service, set up under DARPA, began in 1981.
The limits follow from sharing. Every design must fit the run's process, design rules and fixed schedule, and each participant receives a limited number of dies, so an MPW proves a design or a block of IP while production needs the product's own mask set. Some services share even more finely: Tiny Tapeout collects many very small designs onto one chip, which is then made on a shuttle.
Examples
- An IP vendor checking a new interface block on a TSMC CyberShuttle run before offering it to customers.
- A university group sending a research chip on a Europractice run and paying for a few square millimetres instead of a full mask set.
- A start-up proving its first design on an MPW, then ordering a dedicated mask set for production.
- Students and hobbyists each taking a small tile on a shared Tiny Tapeout chip.
Why it matters
MPWs let universities, start-ups and established chip companies get real silicon early and cheaply, to prove a new circuit, validate IP or a cell library on a new process, or train students. Shuttle programme managers at foundries and brokers, tapeout teams, test chip designers and university staff work with them regularly.
Related terms
Part of the General Industry glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 16 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
Roles
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary