DTCO (Design Technology Co-Optimization)

Notes

DTCO now contributes a majority of the area gain in a typical leading-edge node transition.

Overview

DTCO (design-technology co-optimisation) is the practice of developing a new manufacturing process together with the standard cells, memory bit cells and design rules that will use it, so that gains in density, power and performance come from layout and architecture choices as well as from smaller features. Instead of finishing a process and then handing it to designers, foundries, research centres and EDA companies test candidate devices and rules by building and simulating real cells and blocks. It has become central to scaling as the shrinking of gate and metal pitches slows.

How it works

Early in technology development, teams use TCAD and circuit simulation to design and tune devices, extract compact models, draft layout rules and choose process steps before committing to expensive test wafers. They then design and characterise a trial standard cell library with the draft rules and run block-level evaluations, comparing power, performance and area across the process options.

Many DTCO levers concern the standard cell. Cell height, counted in routing tracks, is a key one: imec reports that gate-all-around nanosheets scale to 5.5-track cells, while stacked complementary FETs (CFETs), which place n-type and p-type transistors on top of each other, could allow 4.5-track cells and eventually 3-track cells. Other levers rearrange gates, source and drain regions and contacts to shrink cells; move power delivery to the back of the wafer to relieve routing congestion and voltage drop; or let designers mix cells with different fin configurations, as in TSMC's FinFlex. imec notes that from the 2 nm generation the scaling of contacted gate pitch and first metal pitch has slowed, which leaves more of the work to such co-optimisation.

The idea is spreading upwards and outwards. System-technology co-optimisation (STCO) applies the same thinking to chiplets, interposers and packages, and some teams now add cost, cycle time and carbon footprint to the usual power, performance and area targets.

Examples

• imec's CFET studies, in which a double-flip sequential CFET option supports 3-track cell libraries with about 98 per cent layout efficiency.
• TSMC's FinFlex, which lets designers mix cells with different fin configurations on one chip.
• Backside power delivery, adopted partly to relieve front-side routing congestion and excessive voltage drop.
• A trial standard cell library built from draft design rules to compare block-level power, performance and area between candidate process options.

Related terms

• STCO
• Cell height
• Fin depopulation
• Transistor density

Where it appears on the Hub

Used on 15 pages of the Hub. In each group, the pages that mention it most come first.