Acronym · EDA Tools & Flows
DRC (Design Rule Check)
Physical verification that compares a layout against the foundry's geometric rule deck for widths, spacings, enclosures, densities and antenna ratios. A clean DRC run against the signed-off deck version is a mandatory tapeout gate.
- Also known as
- Design rule checking
- Type
- Acronym
- Domain
- EDA Tools & Flows, Physical verification
- Also relevant to
- Physical Design & Signoff
Notes
Full-chip DRC at advanced nodes is a multi-thousand-CPU job that can take days, which drives much of the cloud EDA business case.
Overview
DRC (design rule check) is the automated check that a chip layout obeys every geometric rule of the foundry's process, such as minimum widths and spacings, enclosures, densities and antenna limits. It compares every shape in the layout with the foundry's rule deck and reports each violation. A clean DRC run, or one with only approved waivers, against the signed-off rule deck version is a mandatory gate before tapeout.
How it works
The DRC tool reads the layout database and the rule deck, a program written in the tool's rule language that encodes the foundry's design rule manual. It builds derived layers, for example the overlap of two layers or shapes within a certain distance of each other, and measures them against limits. Each violation is reported with its rule name and location so designers can see it on the layout.
Rule decks for advanced processes contain thousands of checks, and some depend on context, such as spacing that changes with the width of nearby wires, or patterns that must be split across masks for multiple patterning. Full-chip runs process billions of shapes, so tools work hierarchically, checking a repeated cell once, and spread the work across many processors.
Teams run DRC continuously: layout engineers check cells and blocks as they draw, place and route tools check as they route, and physical verification engineers run full-chip DRC on the final assembled design, including IP blocks, fill and the seal ring. Violations are fixed, or in rare cases waived with the foundry's agreement. Siemens Calibre, Synopsys IC Validator and Cadence Pegasus are the main commercial tools; KLayout and Magic are used in open flows.
Examples
- A spacing violation between two metal lines found and fixed by rerouting one of them.
- A full-chip DRC run on hundreds of processors in the last week before tapeout.
- A density error fixed by adding metal fill in an empty region.
- A foundry-approved waiver for a known violation inside a licensed memory block.
- KLayout running the open SkyWater 130 nm rule deck in a student project.
Why it matters
A missed DRC error can cause shorts, opens or low yield on every wafer, and finding it after tapeout means new masks. Physical verification, layout and physical design engineers spend much of the final weeks before tapeout closing DRC, and foundries check the results before accepting a design.
Related terms
Part of the EDA Tools & Flows glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 68 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
Roles
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary