Acronym · Lithography & Materials
OPC (Optical Proximity Correction)
Pre-distorting mask shapes, by adding serifs, biasing edges and moving segments, so that the printed result matches the intended layout despite diffraction and process effects.
It is applied as a mandatory post-tapeout step.
- Also known as
- Model-based OPC, MBOPC, RET
- Type
- Acronym
- Domain
- Lithography & Materials, Mask data prep and RET
- Also relevant to
- Physical Design & Signoff
Notes
Full-chip model-based OPC on an advanced layer is one of the largest compute jobs in chip production.
Overview
Optical proximity correction (OPC) deliberately distorts the shapes on a photomask so that, after the blurring and interference of lithography, the pattern printed on the wafer matches what the designer intended. It adds small serifs, moves edges and inserts features too small to print, and is a mandatory step between a finished layout and the masks at every advanced node.

How it works
When features are smaller than the wavelength of light used to print them, the optics cannot reproduce sharp corners and line ends. Corners round, line ends pull back, and the same line prints wider or narrower depending on its neighbours. OPC compensates by changing the mask: adding serifs at corners, extending line ends, biasing edges outwards or inwards, and adding sub-resolution assist features that improve how isolated features print without themselves appearing on the wafer.
Early OPC used fixed rules. Model-based OPC, now standard, uses calibrated models of the optics, the photoresist and sometimes etch to simulate how each edge segment will print, then moves segments iteratively until the simulated result matches the target. A full chip has billions of edges, so OPC runs on large compute clusters. Inverse lithography goes further, computing curved mask shapes that give a more robust result, and depends on mask writers that can produce them.
OPC is part of mask data preparation, done after tapeout by the foundry or mask shop. Verification then checks the corrected mask by simulation for hotspots before the mask is written.
Examples
- Adding hammerhead shapes to line ends so that they print to full length.
- Inserting assist features beside an isolated line so it prints like the same line in a dense array.
- Running model-based OPC on a full chip layer across a large compute cluster before mask writing.
- Using inverse lithography with curved mask shapes for the most critical layers.
Why it matters
Without OPC, advanced chips would not print correctly, and its quality affects yield directly. Computational lithography engineers, mask data preparation engineers and lithography process engineers own it, and designers meet it through DFM rules and lithography-friendly layout. Its compute demands are a notable cost in mask making.
In the chip lifecycle OPC models are built during process development, OPC is applied to each design after tapeout, and models are refined as wafer data accumulates.
It matters most to: Computational Lithography Engineer, DFM Engineer, Layout, Lithography Process Engineer, Mask Data Preparation Engineer
Common confusions
- Not the same as resolution enhancement techniques in general
- OPC is one technique among several, alongside phase-shift masks, off-axis illumination and multiple patterning.
- Not the same as a design change
- OPC changes the mask, not the design intent. The designer's layout stays the reference that the printed result must match.
Sources
- Optical Proximity Correction (OPC) (Knowledge Center) (opens in a new tab), Semiconductor Engineering, 2026-10-22
- Inverse Lithography Technology (ILT) (Knowledge Center) (opens in a new tab), Semiconductor Engineering, 2026-10-22
- The Problem With Proximity (Ed Sperling, 8 April 2010) (opens in a new tab), Semiconductor Engineering, 2026-10-22
- What is Lithography? (opens in a new tab), Synopsys, 2026-10-22
- Optical proximity correction (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
Related terms
Part of the Lithography & Materials glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 38 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
Roles
Skills
Tools
Suggest an improvement
Suggest an improvement to this entry
A clearer definition, an example, a correction or a source an editor can check. Editors review every suggestion before the entry changes.
Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary