A product whose custom logic runs on a commercial FPGA on its own board, from requirements and device selection through logic design, verification, timing closure and board bring-up to system validation, production programming, field updates and the end of life the device's own lifecycle sets. There is no tape-out: the output is a bitstream.
FPGA-based product development lifecycle: 10 stages, 9 gates of its own and 3 hand-offs to the Product lifecycle, from Requirements & Device Selection to Obsolescence & End of Life.
10 stages, 9 gates of its own and 3 hand-offs to the Product lifecycle. Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
In collaboration with The Digital Electronics Blog (opens in a new tab)
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Writing the product requirements, deciding what goes in FPGA logic, in a processor and in software, and choosing an FPGA family and device by its logic, memory, I/O, power, cost and expected availability.
Concept approval gate, owned by the Product lifecycle (Concept approval)Device selected gate
Defining the design's blocks, the vendor and third-party IP cores it uses, clocking and reset, and the pin assignment the board is designed around.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
Writing the logic in a hardware description language or through high-level synthesis and starting to integrate the IP cores and any embedded processor subsystem, while the board is designed in parallel and released for build.
Finishing the logic: the remaining features, the full integration of IP cores and any embedded processor subsystem, code reviews and lint, and trial builds of the whole design for fit and timing, while the first boards are built.
Closing verification on the complete logic in simulation, with clock domain crossing and lint checks and the fixes they lead to, before it is built for hardware, where debugging is slower.
Building the design with the FPGA vendor's tools onto the device's fixed fabric, closing timing against the constraints, and generating the bitstream.
Powering up the first boards, loading the bitstream, bringing up the board support package and drivers, and debugging with on-chip logic analysers.
Testing the whole product against its requirements, and running the compliance tests its market needs, such as electromagnetic compatibility and safety.
Introducing the product to manufacturing, programming and testing each unit, protecting the bitstream and its keys, and proving the route for updating units in the field, up to the production release; field updates then go out through that route while the product is built.
Answering the FPGA vendor's end-of-life notice for the device: assessing the device and the other critical parts, choosing between a last-time buy and moving the design to a newer device, building from last-time-buy stock, and ending field updates, repairs and support in an orderly way, with the design and its build environment archived.
Last-time buy gate, owned by the Product lifecycle (Last-time buy)End of support gate, owned by the Product lifecycle (End of support)
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.