Chip lifecycle / SoC lifecycle / Disciplines / Full-chip physical design

Full-chip physical design (PD)

Turns the full-chip netlist, with each IP block's physical views, into a manufacturable layout and closes timing, power and physical checks.

Active in these stages

SoC Specification & Architecture
IP Integration
SoC RTL Design
Full-Chip Verification
Full-Chip DFT
Physical Design & Sign-off
Tape-out

Roles

Physical Design Engineer →
Place-and-Route Engineer →
Static Timing Analysis Engineer →

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