Component · EDA Tools & Flows
Pcell (Parameterised cell)
A programmable layout cell whose geometry is generated by code from parameters such as width, length, number of fingers or resistor segments. PDKs supply Pcells for every device so designers never draw transistors by hand.
- Also known as
- P-cell, Parameterized cell
- Type
- Component
- Domain
- EDA Tools & Flows, Analog and custom design
Notes
Traditionally written in Cadence SKILL, which is one practical reason PDKs are hard to port away from Virtuoso.
Overview
A Pcell, short for parameterised cell, is a layout cell whose shapes are generated by a program from a set of parameters, such as a transistor's width, length and number of fingers, instead of being drawn by hand. One Pcell can produce every size of a device that a design needs, each drawn consistently to the process's layout rules. Process design kits supply Pcells for their devices, so custom and analogue designers place devices by choosing values rather than drawing polygons.
How it works
Each Pcell has a master: code that declares the parameters, checks or corrects their values, and draws the geometry, for a transistor the diffusion, gate, contacts and metal, according to the process's design rules. When a designer places an instance and sets its parameters, the layout tool runs the code and creates the shapes for that variant. One master serves many instances, which also reduces the design data to be stored. Schematic symbols can be parameterised in the same way, so a device's parameters are set once and carried between schematic and layout.
Pcells are written in the scripting language of the layout environment, most commonly SKILL or Python. The open-source KLayout editor, for example, supports Pcells written as Ruby scripts or compiled libraries, and lets them expose guiding shapes: handles that change a parameter when dragged. Open PDKs show the practice in public: IHP's open 130 nm BiCMOS PDK includes PyCells for KLayout alongside its DRC and LVS rule decks and device models.
Because a Pcell is code, it is tied to the environment that runs it, which is why shared design databases such as OpenAccess, with its plug-in for parameterised designs, matter when one PDK must work in tools from several vendors. A layout exported to a stream format such as GDSII carries only the generated shapes, not the code.
Examples
- A MOSFET Pcell in a foundry PDK that draws a transistor with the chosen width, length and number of fingers.
- IHP's open SG13G2 130 nm BiCMOS PDK, which provides PyCells for the KLayout editor.
- The rounded path Pcell in KLayout's Basic library, controlled by a guiding path and a bend radius parameter.
- A resistor Pcell whose number of segments changes with the requested resistance value.
Why it matters
Pcells make custom layout practical: analogue, RF, memory and I/O layout engineers can place many devices quickly and consistently, and PDK developers spend much of their effort building and qualifying them, because an error in a Pcell repeats in every instance on every design that uses it.
Related terms
Part of the EDA Tools & Flows glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 10 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary