CXL (Compute Express Link)

Notes

Deployment has trailed forecasts because the added latency and software work outweigh the capacity gain for many workloads.

Overview

CXL (Compute Express Link) is an open, cache-coherent interconnect standard, built on the PCI Express physical layer, that lets processors share memory with accelerators and attach extra or pooled memory using ordinary load and store operations. It is managed by the CXL Consortium and is used mainly in servers and data centres to expand and share memory and to connect accelerators efficiently.

How it works

CXL runs three protocols over the same link. CXL.io is essentially PCI Express and handles discovery, configuration and ordinary input and output. CXL.cache lets a device, such as an accelerator, cache host memory coherently. CXL.mem lets the host read and write memory attached to a device as if it were its own. A link switches dynamically between them.

Devices combine these protocols in different ways. Accelerators with their own caches use CXL.io and CXL.cache; accelerators with their own memory add CXL.mem; and memory expansion devices use CXL.io and CXL.mem to add capacity or bandwidth to a server beyond its directly attached DRAM.

Each version has added capability. CXL 2.0 introduced switching and memory pooling, so memory can be allocated to different hosts as needed. CXL 3.x added fabric capabilities and shared memory between hosts, and the CXL Consortium describes CXL 4.0 as doubling bandwidth from 64 GT/s to 128 GT/s. Controllers, switches and memory expander chips implement the standard.

Examples

• A memory expander card that adds DRAM to a server through a CXL link.
• A CXL switch allowing several servers to draw memory from a shared pool.
• An accelerator using CXL.cache to work coherently on data in host memory.
• Verification IP used to check a CXL controller's protocol behaviour before tapeout.

Why it matters

Memory capacity and bandwidth limit many data centre workloads, especially AI, and CXL offers a way to add and share memory without redesigning processors. Server and memory system architects, PCI Express and CXL designers and verification engineers, and memory expander chip designers work with it, and standards representatives shape its evolution.

In the chip lifecycle CXL support is chosen at SoC architecture, implemented with controller and PHY IP, verified with protocol verification IP, and validated for compliance and interoperability on silicon.

Related terms

• Memory pooling
• PCIe
• Persistent memory
• DDR5
• Coherency
• UALink

Where it appears on the Hub

Used on 34 pages of the Hub. In each group, the pages that mention it most come first.