An analog, RF or mixed-signal circuit, such as a data converter, PLL, regulator or radio, from its performance specification through transistor-level design, corner and statistical verification, custom layout and post-layout sign-off to silicon characterisation and production test.
Analog and mixed-signal lifecycle: 8 stages, 9 gates of its own and 3 hand-offs to the Product lifecycle, from AMS Specification & Architecture to Production Test & Qualification.
8 stages, 9 gates of its own and 3 hand-offs to the Product lifecycle, 3 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
In collaboration with The Digital Electronics Blog (opens in a new tab)
A dashed sign with a TR tag is a technical readiness review gate.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Turning product needs into performance targets such as resolution, bandwidth, noise, linearity and power, choosing the circuit topology, and choosing the process and device options it needs.
Concept approval gate, owned by the Product lifecycle (Concept approval)TR1: Process and device readiness gateTR1, technical readiness reviewAMS specification freeze gate
Designing and sizing the circuit at transistor level in schematics, and simulating it against the specification at nominal conditions and the main corners.
Proving the circuit meets its specification across process, voltage and temperature corners and Monte Carlo statistics, and checking it works with the digital logic around it through behavioural models and mixed-signal simulation.
Drawing the layout largely by hand, with device matching, symmetry, guard rings and careful routing of sensitive signals, until it passes design rule and layout versus schematic checks.
Extracting the layout's parasitics and rerunning the key simulations with them, and checking electromigration, IR drop, ESD protection and reliability before release.
Releasing the block either into a larger SoC, with the views and models its integrators need, or as a stand-alone chip or test chip to the foundry.
Measuring the circuit on the bench across supply, temperature and process spread, explaining any difference from simulation, and deriving trim and calibration settings.
Silicon correlated gateEngineering samples gate, owned by the Product lifecycle (Engineering samples)
Measuring analog parameters on every part with a mixed-signal test program, applying trim, qualifying the product for reliability and releasing it to production.
Qualification passed gateTR3, technical readiness reviewProduction release gate, owned by the Product lifecycle (Production release)
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.