SRAM (Static Random Access Memory)

Notes

SRAM bitcell area has scaled far more slowly than logic below 5 nm, making cache a growing share of advanced die area and cost.

Overview

SRAM (static random access memory) is a volatile memory that stores each bit in a small latch made of cross-coupled transistors, holding its value for as long as power is applied without any refresh. It is the fastest memory that can be built in large quantities on a logic chip, which is why it forms the caches, register files and buffers of processors, GPUs and accelerators. Its weakness is size: a cell needs several transistors, so SRAM costs far more area per bit than DRAM or flash.

How it works

The standard cell uses six transistors. Two cross-coupled inverters, four transistors in all, form a latch with two stable states. Two access transistors, switched by a word line, connect the latch to a pair of complementary bit lines. To read, both bit lines are precharged, the word line is raised, and one line dips slightly; a sense amplifier detects the difference. To write, drivers force the bit lines to the new value and overpower the latch.

The cell must be strong enough to keep its value while being read, yet weak enough to be overwritten, and these needs conflict. At low supply voltages, transistor variation can make cells unstable, so designs add read and write assist circuits and set a minimum operating voltage. Variants with eight or more transistors separate the read path for better low-voltage behaviour, and multi-port cells allow simultaneous accesses.

Memory compilers from foundries and IP vendors generate arrays of the size and shape required, in high-speed or high-density flavours, with sleep and shutdown modes, redundancy for repair and hooks for built-in self-test. SRAM bit cells have shrunk much more slowly than logic in recent nodes, so architects increasingly stack extra cache on separate dies, use chiplets on older nodes or consider alternative memories.

Examples

• Level 1, level 2 and last-level caches in a CPU, all built from SRAM arrays.
• AMD's 3D V-Cache, which stacks an extra SRAM die on a processor to enlarge its cache.
• A memory compiler generating many SRAM instances of different sizes for one SoC, each with integrated test and repair.
• Large on-chip SRAM buffers in an AI accelerator that keep weights and activations close to the compute units.
• An SRAM physical unclonable function, which uses the random power-up state of SRAM cells to derive a chip-unique key.

Why it matters

SRAM can take a large share of a processor's die area, so its density, speed, leakage and minimum voltage feed directly into a chip's cost, performance and power. Memory compiler and bit cell designers, foundation IP teams, memory test and repair engineers and architects sizing caches all depend on it.

In the chip lifecycle, cache sizes are set at architecture, memory instances are generated and characterised during design, memory BIST and repair are planned for test, and SRAM minimum voltage and yield are watched closely during qualification and production.

It matters most to: Embedded Memory and SRAM Compiler Design Engineer, Foundation IP Engineer, Memory Characterization Engineer, Memory Compiler Engineer, Memory Test and Repair Engineer

Common confusions

Not the same as DRAM

DRAM stores each bit as charge on a capacitor with one transistor, so it is much denser but slower and must be refreshed. SRAM vs DRAM

Not the same as non-volatile memory

Static means no refresh is needed while powered, not that data survives power loss. SRAM loses its contents when the supply is removed, unlike flash or MRAM.

Not the same as register file

A register file is a small, many-ported storage block inside a processor core. It is often built from SRAM-like cells, but the term names its role, not the cell technology.

Sources

1. SRAM Scaling Issues, And What Comes Next (Karen Heyman, 15 February 2024) (opens in a new tab), Semiconductor Engineering, 2026-10-22
2. Scaling The Lowly SRAM (Mark LaPedus, 5 June 2013) (opens in a new tab), Semiconductor Engineering, 2026-10-22
3. Memory Compilers IP (opens in a new tab), Synopsys, 2026-10-22
4. What is SRAM PUF (Static Random-Access Memory Physical Unclonable Function)? (opens in a new tab), Synopsys, 2026-10-22
5. Static random-access memory (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• 6T bitcell
• DRAM
• Cache
• eDRAM

Where it appears on the Hub

Used on 26 pages of the Hub. In each group, the pages that mention it most come first.