Acronym · EDA Tools & Flows
EDA (Electronic Design Automation)
The software industry and tool category used to design, simulate, verify and lay out integrated circuits. EDA spans RTL synthesis, place and route, circuit simulation, physical verification and signoff analysis, and is the indispensable layer between a chip idea and a manufacturable mask set.
- Also known as
- CAD, ECAD, Design automation
- Type
- Acronym
- Domain
- EDA Tools & Flows, EDA industry
Notes
A roughly 15 billion dollar software market that gates several hundred billion dollars of semiconductor revenue, dominated by three US and German vendors.
Overview
EDA (electronic design automation) is the software, and the industry that makes it, used to design, simulate, verify and prepare chips and circuit boards for manufacture. No modern chip could be designed by hand: EDA tools turn descriptions written by engineers into billions of placed and connected transistors, and check the result against the foundry's rules before any silicon is made.
How it works
EDA tools follow the design flow. Front-end tools cover simulation, formal verification, emulation and prototyping, and logic synthesis. Back-end tools cover placement and routing, parasitic extraction, static timing analysis, power and reliability analysis, and physical verification of the layout. Custom and analogue design uses schematic entry, circuit simulation and hand-guided layout. Test tools insert test logic and generate test patterns, and further tools handle packages, boards and system-level analysis.
The tools depend on foundry data: rule decks, device models and cell libraries from the process design kit, so tool choice and process choice are linked.
Three vendors dominate the market: Synopsys, Cadence and Siemens EDA, which Siemens built on Mentor Graphics after buying it in 2017. Many smaller firms supply specialist tools, open-source flows are used in teaching and with open design kits, and AI is increasingly built into the tools themselves.
Examples
- Logic synthesis in Synopsys Design Compiler, turning RTL into a gate-level netlist.
- Implementation in Synopsys Fusion Compiler, which takes a design from RTL to layout.
- AI-driven optimisation in Synopsys DSO.ai, which searches tool settings for better power, performance and area.
- The open-source OpenROAD flow, which takes a design from RTL to layout and is used with open design kits.
Why it matters
The flow a company builds around its EDA tools shapes its productivity, and the tools are a major cost. CAD and methodology engineers build and support the flows, EDA application engineers help customers use the tools, and licence administrators keep expensive seats in use.
In the chip lifecycle, EDA covers every design stage from architecture modelling to tapeout, and reaches into manufacturing through mask data preparation.
It matters most to:
Related terms
Part of the EDA Tools & Flows glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 256 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
Roles
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary