JEDEC (JEDEC Solid State Technology Association)

Notes

Founded in 1958 as a joint EIA/NEMA activity; the DDR, LPDDR, HBM, UFS and e-MMC families all originate here.

Overview

JEDEC (the JEDEC Solid State Technology Association) is the standards body whose member companies write the specifications that define memory chips, memory modules and many packaging and reliability test methods for the semiconductor industry. DDR and LPDDR memory, high bandwidth memory, flash interfaces and widely used qualification tests all come from JEDEC committees. Its published standards can be downloaded free of charge after registration.

How it works

JEDEC began as the Joint Electron Device Engineering Council, formed in 1958, and is now an independent association. Work is done in technical committees made up of member companies, chip makers, system companies, equipment and test suppliers. The memory committee, JC-42, and its subcommittees write the DRAM standards, including DDR5 and the HBM family; other committees cover flash, reliability test methods, packaging outlines and the electrostatic discharge tests it publishes jointly with the ESD Association.

A standard starts as proposals from members, which a committee debates, revises and ballots. Members disclose patents that may be essential and commit to licensing terms, so that companies can build compatible products. Once approved, the standard is published and later revised as the technology moves on, with letters after the number marking revisions.

Because memory from different suppliers must work in the same sockets and systems, JEDEC standards are what let a server or phone maker buy DRAM from several vendors. Reliability standards, such as stress tests and moisture sensitivity classification, are used by suppliers to qualify parts and by customers to set requirements.

Examples

• The DDR5 SDRAM standard that defines how memory chips and controllers communicate in servers and PCs.
• The HBM4 standard for stacked high bandwidth memory used beside AI processors.
• J-STD-020, the joint IPC and JEDEC standard for classifying how sensitive surface-mount parts are to moisture during reflow.
• JS-001, the joint human body model electrostatic discharge test published with the ESD Association.
• A controller IP vendor sending engineers to JC-42 meetings to follow the next memory generation.

Why it matters

Memory designers, controller and PHY designers, packaging engineers and reliability engineers work to JEDEC standards every day, and many companies send representatives to its committees to shape them. A product that does not meet the relevant JEDEC standard usually cannot be sold into mainstream memory markets.

Related terms

• JESD79
• JESD209
• JESD235
• JESD22
• EIA
• J-STD-020

Where it appears on the Hub

Used on 112 pages of the Hub. In each group, the pages that mention it most come first.