Chip lifecycle / Process node lifecycle / PDK & Design Enablement Development

PDK & Design Enablement Development

Building the process design kit from the baseline: device models, the design rule manual, physical verification and extraction decks and technology files, released in versions of rising maturity, with the foundation libraries started alongside. The PDK development lifecycle follows the kit's own build, release and support in detail.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^A04 Process Integration & Baseline

^D05 PDK & Design Enablement DevelopmentYou are here

^DA06 Test Chips & Yield Learning

Business and customers milestones

DSDesign-start PDK release PPPre-production PDK release

Technology milestones

MCProcess modules capable BFTR2Process baseline freeze YRYield readiness

Technology business and roadmap^A

v0.1

v0.5

Device engineering and modelling^A

v0.1

v0.5^D

Design-technology co-optimisation^A

v0.1

v0.5

Lithography and patterning^A

v0.1^A

v0.5

Process module engineering^A

v0.1

v0.5

Process integration^A

v0.1

v0.5

Test chips and electrical test^A

v0.1

v0.5

Yield, defects and process control^D

v0.1^D

v0.5

^DAA

Process reliability and quality^A

v0.5

PDK development and release^A

v0.1

v0.5^A

Foundation IP and libraries^O

v0.1

v0.5

Customer design enablement and ecosystem^A

v0.1

v0.5

Manufacturing operations and capacity^O

v0.1

v0.5

Equipment and materials supply^A

v0.1

v0.5

KeyPre-kitPathfindingv0.1Early access kitv0.5Design-start kitv0.9Pre-production kitv1.0Production kitHVMIn volume productionFaded block: Held, the status shown before it still standsFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.You are here: PDK & Design Enablement DevelopmentAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

Show this chart as a list

Stages

Process Integration & Baseline^A
PDK & Design Enablement Development (this stage)^D
Test Chips & Yield Learning^DA

Business and customers milestones

Technology milestones

Process modules capable (MC)
Process baseline freeze (BF) (technical readiness review TR2)
Yield readiness (YR)

Disciplines

Technology business and roadmap^A
- Process Integration & Baseline: maturity v0.1, Early access kit. Business case, investment plan and node market requirements approved at the technology definition, with investment tracked as modules are built.
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Investment tracked against the plan while the baseline and the design-start kit are built, and early customer interest gathered.
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Investment tracked against the plan while the baseline and the design-start kit are built, and early customer interest gathered.
Device engineering and modelling^A
- Process Integration & Baseline: maturity v0.1, Early access kit. Device targets set and handed to the kit as target models, and early silicon characterised as modules come up.
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Devices characterised on the baseline flow and compact models fitted to its silicon for the design-start kit.^D
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Devices characterised on the baseline flow and compact models fitted to its silicon for the design-start kit.; Models correlated to silicon
Design-technology co-optimisation^A
- Process Integration & Baseline: maturity v0.1, Early access kit. Co-optimisation study and design rule intent handed to the technology definition and the early access kit.
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Block-level benchmarks run on the frozen baseline and handed over with the design-start kit.
Lithography and patterning^A
- Process Integration & Baseline: maturity v0.1, Early access kit. Patterning solution developed and OPC models built while the modules are made capable, then test vehicle masks released.^A
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Hotspots learned from baseline and test chip wafers and fed back to the rules and OPC.
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Hotspots learned from baseline and test chip wafers and fed back to the rules and OPC.
Process module engineering^A
- Process Integration & Baseline: maturity v0.1, Early access kit. Process modules developed to their specifications and proven capable for integration.
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Module specifications released into the frozen baseline and held under change control while the kit is fitted.
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Module specifications released into the frozen baseline and held under change control while the kit is fitted.
Process integration^A
- Process Integration & Baseline: maturity v0.1, Early access kit. Technology definition written and the integrated flow assembled from the modules with short-loop learning.; Baseline frozen
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Integrated flow and process baseline frozen, then integration learning run on test chip lots.
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Integrated flow and process baseline frozen, then integration learning run on test chip lots.
Test chips and electrical test^A
- Process Integration & Baseline: maturity v0.1, Early access kit. Test vehicle plan written, first parametric data taken from short loops and test vehicles designed for the baseline.
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Test chips measured on the baseline flow, with parametric data feeding the models and yield learning.
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Test chips measured on the baseline flow, with parametric data feeding the models and yield learning.
Yield, defects and process control^D
- Process Integration & Baseline: maturity v0.1, Early access kit. Inline control plan drafted for the baseline flow.^D
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Defect and yield learning run on test chip lots against the yield model.
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Defect and yield learning run on test chip lots against the yield model.^D
Process reliability and quality^A
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Reliability test plan written and early stress run on baseline test chips.
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Reliability test plan written and early stress run on baseline test chips.
PDK development and release^A
- Process Integration & Baseline: maturity v0.1, Early access kit. Early access kit released on target models and the draft rule manual.
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Design-start kit released with models fitted to baseline silicon and decks checked on test layouts.^A
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Design-start kit released with models fitted to baseline silicon and decks checked on test layouts.
Foundation IP and libraries^O
- Process Integration & Baseline: maturity v0.1, Early access kit. Library development started on the early access kit.
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Foundation libraries handed over on the design-start kit and developed towards final.
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Foundation libraries handed over on the design-start kit and developed towards final.
Customer design enablement and ecosystem^A
- Process Integration & Baseline: maturity v0.1, Early access kit. Early customers and partners engaged on the early access kit.
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Engagement continued on the design-start kit, with the reference flow and the shuttle plan in preparation.
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Engagement continued on the design-start kit, with the reference flow and the shuttle plan in preparation.
Manufacturing operations and capacity^O
- Process Integration & Baseline: maturity v0.1, Early access kit. Cost of ownership model and first capacity plan set for the technology definition.
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Capacity plan tracked while the baseline and the kit mature, with no production commitment yet.
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Capacity plan tracked while the baseline and the kit mature, with no production commitment yet.
Equipment and materials supply^A
- Process Integration & Baseline: maturity v0.1, Early access kit. Tools and materials developed with suppliers for the process modules.
- PDK & Design Enablement Development: maturity v0.5, Design-start kit. Supplier readiness tracked as the frozen baseline is used on test chip lots.
- Test Chips & Yield Learning: maturity v0.5, Design-start kit. Supplier readiness tracked as the frozen baseline is used on test chip lots.

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