Chip lifecycle
The Chip Development Lifecycle
A semiconductor product lives through a product lifecycle, from the first sign of a market opportunity to the end of support after its last shipment. The product lifecycle is the umbrella. The 35 engineering lifecycles run inside it, in 7 families: chip and IP design; systems and platforms; software, security and AI; process, packaging and manufacturing; regulated markets; quality and process assessment; and building a chip company. Chip and IP design includes the SoC, Soft IP and Hard IP lifecycles. Each has its own stages, gates and disciplines, and the map below shows every one. The AI-assisted flow adoption lifecycle also has a view of where AI assistance applies across every lifecycle.
Explainer: The Product Lifecycle (PLC): How MRDs, PRDs, and Stage-Gate Reviews Work →Start here: the lifecycle in five steps
A short path through the lifecycle content on the Hub, from the whole picture to the checks and the training for your role.
- Step 1The whole lifecycle at a glanceEvery chip lifecycle on the Hub drawn into one view, from planning and concept to end of life.11 generic phases
- Step 2The product lifecycle, from opportunity to end of lifeHow a semiconductor product is decided, built, launched, sustained and retired, with the business disciplines at each stage.13 stages and 31 gates
- Step 3Find the lifecycle for what you buildAnswer a few questions about your product in the product type classifier, or pick from the list of lifecycles.36 lifecyclesThe list of lifecycles
- Step 4Gates, checklists and work productsWhat is checked at each gate and what is handed over, with the checklists to run and the work products to prepare.683 gates, 2,079 checklists and 2,298 work productsAll work products
- Step 5Training plans for your roleA plan for each kind of member, built on the lifecycles, stage guides, gate packs and checklists.20 training plans
What you will find in the lifecycle area
Every number is counted from the lifecycle content on the Hub today.
- 683GatesThe decisions that close the 432 stages, each with what is checked and handed over.
- 2,079ChecklistsReady to run at each stage and gate, with 64,683 checks between them.
- 2,298Work productsThe documents, models and items brought to the gates: who makes them and who uses them.
- 28TimelinesLifecycles with indicative durations by complexity, from 132 cited ranges.
- 424Key risksRisks and mitigations across 36 lifecycles, including supply chain and export control.
- 7OverlaysCross-cutting practices laid over every lifecycle, 90 practices in all.
- 901AI impact notesWhere AI is disrupting, augmenting or opening up the work at a stage, gate or discipline.
- 20Training plansA plan for each kind of member, built on the lifecycles, guides and checklists.
Every lifecycle on the Hub, by family
36 lifecycles with 432 stages and 683 gates between them, one row per family. Each strip is a lifecycle's stages in order, with its gates marked above the stage they open or close; select a lifecycle to open its overview.
The umbrella
The product lifecycle every other lifecycle sits inside.1lifecycle13stages31gates- Product lifecycleThe business lifecycle of a semiconductor product, from the first sign of a market opportunity through concept, definition, development, validation, sampling, qualification, launch, ramp, maturity and decline to end of life and the support that continues after the last shipment.13 stages31 gates
Chip and IP design
Lifecycles for building a kind of chip or the blocks inside it.14lifecycles165stages271gates- SoC and full-chip lifecycleThe whole chip, from its specification through IP integration, full-chip design and verification, tape-out, bring-up and qualification to production and end of life.15 stages22 gates3 TR reviews
- Soft IP lifecycleOne reusable block delivered as synthesisable design code (soft IP), made in-house or taken in from a supplier, from its specification through design, verification, implementation views and quality checks to a versioned release for SoC teams.8 stages10 gates2 TR reviews
- Hard IP lifecycleFor the circuit design, layout, verification, characterisation, test chip, validation, reliability and release teams who build a hard macro (a block delivered as a laid out GDS for one process, such as an interface PHY, a memory, a clock or an analog block) and prove it on a test chip before integrators use it.9 stages16 gates3 TR reviews
- Analog and mixed-signal lifecycleFor converters, references, regulators, clocks and radios, designed at transistor level.8 stages12 gates3 TR reviews
- Chiplet and advanced packaging lifecycleFor products built from several dies joined in one package.9 stages13 gates3 TR reviews
- FPGA-based product development lifecycleFor products whose custom logic runs on a commercial FPGA instead of a custom chip.10 stages12 gates
- FPGA chip development lifecycleFor the architecture, circuit, configuration and security, verification, physical design, design software, characterisation, test, quality and product teams at an FPGA vendor who develop the device family itself: its fabric, hard IP, bitstream security, speed grades and the place-and-route and timing software customers design with.13 stages24 gates3 TR reviews
- Structured ASIC lifecycleFor the architecture, library, physical design, verification, test, quality, supply and customer engineering teams who build a structured ASIC platform on a pre-built base array, and for the customers whose designs, often first proven on an FPGA, are customised on it in a few metal or via layers.15 stages30 gates3 TR reviews
- AI accelerator lifecycleFor chips built to train or run machine learning models, developed together with their compiler, runtime, libraries and the systems they run in.14 stages23 gates3 TR reviews
- Memory product lifecycle (DRAM, NAND and HBM)For memory makers' product, design, process, test, packaging and quality teams taking a DRAM, NAND or HBM generation from roadmap and cell choice to volume, grades, shrinks and end of life, and for the system, package and processor teams who qualify and integrate the parts.14 stages22 gates3 TR reviews
- RF and mmWave product lifecycleFor the RF, millimetre-wave, electromagnetic, module, antenna, measurement, compliance and test teams who take a front-end module, transceiver, power amplifier, filter or phased array from its bands and standards to certification, production and end of life.12 stages22 gates3 TR reviews
- Silicon photonics and optical interconnect lifecycleFor the photonic, electronic, packaging, test and reliability teams who take a silicon photonics product, such as an optical engine, a transceiver, co-packaged optics or an optical sensing chip, from its application and link budget through laser integration, wafer-level optical test and fibre attach to qualification, volume and end of life.13 stages20 gates3 TR reviews
- Power and compound semiconductor lifecycleFor the device, process, materials, packaging, reliability, applications and quality teams who take a silicon carbide, gallium nitride or silicon power device or module from the application it serves to qualified volume supply, and for the inverter, charger and power supply designers who design it in.13 stages24 gates3 TR reviews
- MEMS and sensors lifecycleFor the MEMS, ASIC, packaging, calibration, test and reliability teams who develop motion, pressure, acoustic, environmental and image sensors, where the transducer, its process, its interface chip and its package are designed together and every unit is calibrated.12 stages21 gates3 TR reviews
Systems and platforms
Taking chips into finished systems, and building the shared platforms that many products are derived from.2lifecycles24stages39gates- System development lifecycleFor the system architects, systems engineers, board, mechanical, firmware, software, prototyping, integration, validation, compliance, manufacturing and support teams who take a product built around one or more chips from its requirements and the split between hardware, software and firmware to a validated, certified and supported system.12 stages21 gates3 TR reviews
- Platform and derivative products lifecycleFor the platform architects, portfolio and product managers, IP, software, firmware, tools, prototyping, verification and derivative teams who build a shared base of architecture, IP, software and tools once and derive several products from it, and support all of them over the platform's life.12 stages18 gates3 TR reviews
Software, security and AI
The firmware, the security of the chip and the AI-assisted steps in the flow.3lifecycles37stages53gates- Firmware and software stack lifecycleFor the teams who write and support the boot code, firmware, drivers, SDKs and security of a chip's software stack, and for hardware teams who need to know which of their milestones the software depends on and which it gates.12 stages17 gates
- Chip and product security lifecycleFor hardware security architects, cryptography, verification and evaluation engineers, firmware, supply chain, certification, compliance and incident response teams who take a chip and its product from security objectives and a threat model through a secure architecture, attack testing, secure provisioning and certification to vulnerability response, security updates and the end of security support.13 stages19 gates
- AI-assisted design flow adoption lifecycleFor CAD and flow teams, design and verification leads, IT security, legal and quality who bring an AI-assisted tool into a design flow, and need it qualified, governed and accountable before anyone relies on it.12 stages17 gates
Process, packaging and manufacturing
The process, design kit, package, fab, tools and test program the chips depend on.6lifecycles74stages113gates- Process technology (node) lifecycleFor foundries and chipmakers developing a manufacturing process and its design kit, and for the design teams who build on it.12 stages18 gates3 TR reviews
- Process design kit (PDK) development lifecycleFor the teams who build, release and support a process design kit and its foundation IP libraries, and for the design teams who need to know which kit release their work can rely on.13 stages16 gates3 TR reviews
- Package technology development lifecycleFor the assembly and test providers, foundry packaging groups, materials and equipment suppliers and lead customers who develop a new package technology, such as fine-pitch bumping, redistribution layers, interposers or hybrid bonding, and take it from customer drivers and test vehicles through qualification and a design kit to volume and end of life.12 stages19 gates3 TR reviews
- Fab build and equipment qualification lifecycleFor the investment, site, facilities, equipment, process, quality, operations and workforce teams who plan, build, equip, qualify and ramp a semiconductor fab or a new phase of one, and for the governments, suppliers and customers who work with them.12 stages20 gates3 TR reviews
- Semiconductor equipment lifecycleFor the product, systems, process, mechanical, electrical, optics, software, integration, reliability and safety, supply chain, field service and trade compliance teams of an equipment maker who take a deposition, etch, lithography, metrology, test or assembly tool from customer roadmaps and requirements through alpha and beta evaluations and customer qualification to production, installed base service, upgrades and end of support, and for the fab and packaging teams who evaluate and run it.13 stages20 gates3 TR reviews
- Test program and ATE development lifecycleFor the test, product and DFT engineers who decide how a chip is tested in manufacturing and who build, release and maintain its test program, patterns and test hardware.12 stages20 gates
Regulated markets
Chips for markets with their own safety, reliability and approval rules.6lifecycles73stages107gates- Automotive and safety-critical lifecycleFor chips that go into vehicles and other safety-critical systems, developed to ISO 26262 and qualified to AEC-Q100.13 stages18 gates3 TR reviews
- Vehicle cybersecurity and software update lifecycleFor vehicle makers, tier one suppliers and the chip, IP and software suppliers behind them who set up a cybersecurity management system, analyse threats, design, verify and validate security, support cybersecurity type approval under UN R155, run software updates under UN R156, and monitor, respond to and support their products until the end of cybersecurity support.13 stages19 gates
- Space and radiation-hardened parts lifecycleFor teams designing, testing, screening, qualifying and supplying parts for spacecraft and other radiation environments, hardened by process, by design or both, and for the programs that depend on their supply.12 stages20 gates3 TR reviews
- Avionics and airborne electronics lifecycleFor the systems, safety, hardware, software, verification, certification, process assurance, configuration, component and production teams who take airborne electronic hardware and software from aircraft and system requirements and assigned assurance levels through certification plans, design, verification, qualification and the final compliance review to production, continued airworthiness and end of support, and for the chip and IP suppliers whose parts go into it.11 stages14 gates3 TR reviews
- Medical electronics and medical device chips lifecycleFor the systems, chip, hardware, software, security, usability, test, quality, risk management, regulatory affairs, manufacturing and post-market teams who take a medical device, or a chip designed for one, from its intended use and regulatory strategy through design controls, risk management, electrical safety and EMC testing, usability validation and regulatory submission to production, post-market surveillance and end of support.12 stages19 gates3 TR reviews
- Industrial and energy electronics lifecycleFor the product, functional safety, security, hardware, chip, firmware, compliance, test, manufacturing, field and supply teams who take a controller, drive, inverter, protection relay, sensor interface or the chips inside them from the application and its hazards through a functional safety lifecycle and a secure development process to assessment, certification, long-life supply and end of support, and for the integrators and asset owners who build them into safety systems, machinery, plants and grids.12 stages17 gates3 TR reviews
Quality and process assessment
The quality system and the process and supplier approval schemes around the work.3lifecycles31stages42gates- Quality management system lifecycle (ISO 9001 and IATF 16949)For top management, quality systems managers, process owners, internal auditors, customer and supplier quality engineers and problem solving leads who build, certify and run a quality management system to ISO 9001, and to IATF 16949 where automotive production parts are supplied, through internal audits, management reviews, certification, surveillance and recertification.10 stages12 gates
- APQP and PPAP lifecycleFor automotive program, customer quality, product, reliability, process, quality, metrology, test, supplier quality, logistics and change control teams who plan the quality of a new automotive part with APQP, get it approved through PPAP, launch it safely and keep it approved through every later change until the end of production.9 stages14 gates
- Automotive SPICE process and assessment lifecycleFor quality, process, project, system, software, hardware and test teams of automotive suppliers, including chip, IP and software suppliers, who have to show their customers process capability to Automotive SPICE, and for the sponsors who fund the improvement work and the assessors who rate it.12 stages16 gates
Building a chip company
A fabless startup from founding to its first product in volume.1lifecycle15stages27gates- Fabless startup chip lifecycleFor founders, early employees and investors of a new fabless chip company, taking a first chip from a thesis through a test chip and design partners to product silicon and first revenue, with each funding round beside the engineering gates.15 stages27 gates3 TR reviews
stages, first to last a gatea technical readiness review (TR) the design release, such as tape-out the production releaseFamilies are the Hub's own grouping, for reading the map.
Show this chart as a list
The umbrella: 1 lifecycle, 13 stages, 31 gates
- Product lifecycle: 13 stages and 31 gates, production release at Production release; 11 disciplines. The business lifecycle of a semiconductor product, from the first sign of a market opportunity through concept, definition, development, validation, sampling, qualification, launch, ramp, maturity and decline to end of life and the support that continues after the last shipment.
Chip and IP design: 14 lifecycles, 165 stages, 271 gates
- SoC and full-chip lifecycle: 15 stages and 22 gates, 3 technical readiness reviews, design release at Tape-out, production release at Production release; 17 disciplines. The whole chip, from its specification through IP integration, full-chip design and verification, tape-out, bring-up and qualification to production and end of life.
- Soft IP lifecycle: 8 stages and 10 gates, 2 technical readiness reviews; 12 disciplines. One reusable block delivered as synthesisable design code (soft IP), made in-house or taken in from a supplier, from its specification through design, verification, implementation views and quality checks to a versioned release for SoC teams.
- Hard IP lifecycle: 9 stages and 16 gates, 3 technical readiness reviews, design release at Test chip tape-out; 13 disciplines. For the circuit design, layout, verification, characterisation, test chip, validation, reliability and release teams who build a hard macro (a block delivered as a laid out GDS for one process, such as an interface PHY, a memory, a clock or an analog block) and prove it on a test chip before integrators use it.
- Analog and mixed-signal lifecycle: 8 stages and 12 gates, 3 technical readiness reviews, design release at Tape-out or SoC hand-off, production release at Production release; 12 disciplines. For converters, references, regulators, clocks and radios, designed at transistor level.
- Chiplet and advanced packaging lifecycle: 9 stages and 13 gates, 3 technical readiness reviews, design release at Multi-die tape-out, production release at Production release; 12 disciplines. For products built from several dies joined in one package.
- FPGA-based product development lifecycle: 10 stages and 12 gates, design release at Timing closure and bitstream, production release at Production release; 11 disciplines. For products whose custom logic runs on a commercial FPGA instead of a custom chip.
- FPGA chip development lifecycle: 13 stages and 24 gates, 3 technical readiness reviews, design release at Tape-out, production release at Production release; 14 disciplines. For the architecture, circuit, configuration and security, verification, physical design, design software, characterisation, test, quality and product teams at an FPGA vendor who develop the device family itself: its fabric, hard IP, bitstream security, speed grades and the place-and-route and timing software customers design with.
- Structured ASIC lifecycle: 15 stages and 30 gates, 3 technical readiness reviews, design release at Base layer tape-out and Custom layer tape-out, production release at Production release; 16 disciplines. For the architecture, library, physical design, verification, test, quality, supply and customer engineering teams who build a structured ASIC platform on a pre-built base array, and for the customers whose designs, often first proven on an FPGA, are customised on it in a few metal or via layers.
- AI accelerator lifecycle: 14 stages and 23 gates, 3 technical readiness reviews, design release at Tape-out, production release at Production release; 16 disciplines. For chips built to train or run machine learning models, developed together with their compiler, runtime, libraries and the systems they run in.
- Memory product lifecycle (DRAM, NAND and HBM): 14 stages and 22 gates, 3 technical readiness reviews, design release at Tape-out, production release at Production release; 14 disciplines. For memory makers' product, design, process, test, packaging and quality teams taking a DRAM, NAND or HBM generation from roadmap and cell choice to volume, grades, shrinks and end of life, and for the system, package and processor teams who qualify and integrate the parts.
- RF and mmWave product lifecycle: 12 stages and 22 gates, 3 technical readiness reviews, design release at Tape-out, production release at Production release; 15 disciplines. For the RF, millimetre-wave, electromagnetic, module, antenna, measurement, compliance and test teams who take a front-end module, transceiver, power amplifier, filter or phased array from its bands and standards to certification, production and end of life.
- Silicon photonics and optical interconnect lifecycle: 13 stages and 20 gates, 3 technical readiness reviews, design release at Tape-out, production release at Production release; 13 disciplines. For the photonic, electronic, packaging, test and reliability teams who take a silicon photonics product, such as an optical engine, a transceiver, co-packaged optics or an optical sensing chip, from its application and link budget through laser integration, wafer-level optical test and fibre attach to qualification, volume and end of life.
- Power and compound semiconductor lifecycle: 13 stages and 24 gates, 3 technical readiness reviews, design release at Process baseline freeze, production release at Production part approval and release; 13 disciplines. For the device, process, materials, packaging, reliability, applications and quality teams who take a silicon carbide, gallium nitride or silicon power device or module from the application it serves to qualified volume supply, and for the inverter, charger and power supply designers who design it in.
- MEMS and sensors lifecycle: 12 stages and 21 gates, 3 technical readiness reviews, design release at Qualification start, production release at Production release; 15 disciplines. For the MEMS, ASIC, packaging, calibration, test and reliability teams who develop motion, pressure, acoustic, environmental and image sensors, where the transducer, its process, its interface chip and its package are designed together and every unit is calibrated.
Systems and platforms: 2 lifecycles, 24 stages, 39 gates
- System development lifecycle: 12 stages and 21 gates, 3 technical readiness reviews, design release at System design freeze, production release at Production release; 16 disciplines. For the system architects, systems engineers, board, mechanical, firmware, software, prototyping, integration, validation, compliance, manufacturing and support teams who take a product built around one or more chips from its requirements and the split between hardware, software and firmware to a validated, certified and supported system.
- Platform and derivative products lifecycle: 12 stages and 18 gates, 3 technical readiness reviews, design release at Platform baseline released, production release at Derivative production release; 15 disciplines. For the platform architects, portfolio and product managers, IP, software, firmware, tools, prototyping, verification and derivative teams who build a shared base of architecture, IP, software and tools once and derive several products from it, and support all of them over the platform's life.
Software, security and AI: 3 lifecycles, 37 stages, 53 gates
- Firmware and software stack lifecycle: 12 stages and 17 gates, design release at Early-access SDK, production release at Production software release; 15 disciplines. For the teams who write and support the boot code, firmware, drivers, SDKs and security of a chip's software stack, and for hardware teams who need to know which of their milestones the software depends on and which it gates.
- Chip and product security lifecycle: 13 stages and 19 gates, design release at Security verification sign-off; 15 disciplines. For hardware security architects, cryptography, verification and evaluation engineers, firmware, supply chain, certification, compliance and incident response teams who take a chip and its product from security objectives and a threat model through a secure architecture, attack testing, secure provisioning and certification to vulnerability response, security updates and the end of security support.
- AI-assisted design flow adoption lifecycle: 12 stages and 17 gates, production release at Production flow release; 13 disciplines. For CAD and flow teams, design and verification leads, IT security, legal and quality who bring an AI-assisted tool into a design flow, and need it qualified, governed and accountable before anyone relies on it.
Process, packaging and manufacturing: 6 lifecycles, 74 stages, 113 gates
- Process technology (node) lifecycle: 12 stages and 18 gates, 3 technical readiness reviews; 15 disciplines. For foundries and chipmakers developing a manufacturing process and its design kit, and for the design teams who build on it.
- Process design kit (PDK) development lifecycle: 13 stages and 16 gates, 3 technical readiness reviews, production release at Production PDK release; 15 disciplines. For the teams who build, release and support a process design kit and its foundation IP libraries, and for the design teams who need to know which kit release their work can rely on.
- Package technology development lifecycle: 12 stages and 19 gates, 3 technical readiness reviews; 17 disciplines. For the assembly and test providers, foundry packaging groups, materials and equipment suppliers and lead customers who develop a new package technology, such as fine-pitch bumping, redistribution layers, interposers or hybrid bonding, and take it from customer drivers and test vehicles through qualification and a design kit to volume and end of life.
- Fab build and equipment qualification lifecycle: 12 stages and 20 gates, 3 technical readiness reviews; 14 disciplines. For the investment, site, facilities, equipment, process, quality, operations and workforce teams who plan, build, equip, qualify and ramp a semiconductor fab or a new phase of one, and for the governments, suppliers and customers who work with them.
- Semiconductor equipment lifecycle: 13 stages and 20 gates, 3 technical readiness reviews, production release at Production release; 15 disciplines. For the product, systems, process, mechanical, electrical, optics, software, integration, reliability and safety, supply chain, field service and trade compliance teams of an equipment maker who take a deposition, etch, lithography, metrology, test or assembly tool from customer roadmaps and requirements through alpha and beta evaluations and customer qualification to production, installed base service, upgrades and end of support, and for the fab and packaging teams who evaluate and run it.
- Test program and ATE development lifecycle: 12 stages and 20 gates, design release at Test program ready for silicon, production release at Production test release; 15 disciplines. For the test, product and DFT engineers who decide how a chip is tested in manufacturing and who build, release and maintain its test program, patterns and test hardware.
Regulated markets: 6 lifecycles, 73 stages, 107 gates
- Automotive and safety-critical lifecycle: 13 stages and 18 gates, 3 technical readiness reviews, design release at Tape-out, production release at Production release; 15 disciplines. For chips that go into vehicles and other safety-critical systems, developed to ISO 26262 and qualified to AEC-Q100.
- Vehicle cybersecurity and software update lifecycle: 13 stages and 19 gates, production release at Release for post-development; 13 disciplines. For vehicle makers, tier one suppliers and the chip, IP and software suppliers behind them who set up a cybersecurity management system, analyse threats, design, verify and validate security, support cybersecurity type approval under UN R155, run software updates under UN R156, and monitor, respond to and support their products until the end of cybersecurity support.
- Space and radiation-hardened parts lifecycle: 12 stages and 20 gates, 3 technical readiness reviews, design release at Tape-out; 15 disciplines. For teams designing, testing, screening, qualifying and supplying parts for spacecraft and other radiation environments, hardened by process, by design or both, and for the programs that depend on their supply.
- Avionics and airborne electronics lifecycle: 11 stages and 14 gates, 3 technical readiness reviews, design release at Final compliance review; 12 disciplines. For the systems, safety, hardware, software, verification, certification, process assurance, configuration, component and production teams who take airborne electronic hardware and software from aircraft and system requirements and assigned assurance levels through certification plans, design, verification, qualification and the final compliance review to production, continued airworthiness and end of support, and for the chip and IP suppliers whose parts go into it.
- Medical electronics and medical device chips lifecycle: 12 stages and 19 gates, 3 technical readiness reviews, design release at Design verification complete, production release at Production release; 14 disciplines. For the systems, chip, hardware, software, security, usability, test, quality, risk management, regulatory affairs, manufacturing and post-market teams who take a medical device, or a chip designed for one, from its intended use and regulatory strategy through design controls, risk management, electrical safety and EMC testing, usability validation and regulatory submission to production, post-market surveillance and end of support.
- Industrial and energy electronics lifecycle: 12 stages and 17 gates, 3 technical readiness reviews, design release at Type test readiness, production release at Production release; 14 disciplines. For the product, functional safety, security, hardware, chip, firmware, compliance, test, manufacturing, field and supply teams who take a controller, drive, inverter, protection relay, sensor interface or the chips inside them from the application and its hazards through a functional safety lifecycle and a secure development process to assessment, certification, long-life supply and end of support, and for the integrators and asset owners who build them into safety systems, machinery, plants and grids.
Quality and process assessment: 3 lifecycles, 31 stages, 42 gates
- Quality management system lifecycle (ISO 9001 and IATF 16949): 10 stages and 12 gates; 11 disciplines. For top management, quality systems managers, process owners, internal auditors, customer and supplier quality engineers and problem solving leads who build, certify and run a quality management system to ISO 9001, and to IATF 16949 where automotive production parts are supplied, through internal audits, management reviews, certification, surveillance and recertification.
- APQP and PPAP lifecycle: 9 stages and 14 gates; 12 disciplines. For automotive program, customer quality, product, reliability, process, quality, metrology, test, supplier quality, logistics and change control teams who plan the quality of a new automotive part with APQP, get it approved through PPAP, launch it safely and keep it approved through every later change until the end of production.
- Automotive SPICE process and assessment lifecycle: 12 stages and 16 gates; 12 disciplines. For quality, process, project, system, software, hardware and test teams of automotive suppliers, including chip, IP and software suppliers, who have to show their customers process capability to Automotive SPICE, and for the sponsors who fund the improvement work and the assessors who rate it.
Building a chip company: 1 lifecycle, 15 stages, 27 gates
- Fabless startup chip lifecycle: 15 stages and 27 gates, 3 technical readiness reviews, design release at Test chip tape-out and Product tape-out, production release at Production release; 23 disciplines. For founders, early employees and investors of a new fabless chip company, taking a first chip from a thesis through a test chip and design partners to product silicon and first revenue, with each funding round beside the engineering gates.
The product lifecycle, and where the other lifecycles fit
The product lifecycle runs across the top; select a stage to open it, or an explainer under it. Each band below is an engineering lifecycle or an explainer framework, placed under the product stages it fits.
Product lifecycle
Engineering lifecycles inside it
Frameworks the explainers describe
Show this chart as a table
| Lifecycle | Product stages it spans |
|---|---|
| SoC lifecycle | Concept & Business Case to End of Life |
| Soft IP lifecycle | Definition & Planning to Development |
| Hard IP lifecycle | Definition & Planning to Post-EOL Support |
| AMS lifecycle | Definition & Planning to Qualification & Production Readiness |
| Chiplet lifecycle | Definition & Planning to Qualification & Production Readiness |
| FPGA lifecycle | Definition & Planning to Post-EOL Support |
| Automotive lifecycle | Definition & Planning to Post-EOL Support |
| AI accelerator lifecycle | Concept & Business Case to Post-EOL Support |
| Process node lifecycle | Opportunity & Market Sensing to Post-EOL Support |
| PDK lifecycle | Concept & Business Case to Post-EOL Support |
| Firmware and software lifecycle | Concept & Business Case to Post-EOL Support |
| Test program lifecycle | Definition & Planning to Post-EOL Support |
| Startup lifecycle | Opportunity & Market Sensing to Maturity & Sustaining |
| AI-assisted flow lifecycle | Concept & Business Case to Post-EOL Support |
| Memory lifecycle | Opportunity & Market Sensing to Post-EOL Support |
| Space lifecycle | Concept & Business Case to Post-EOL Support |
| Photonics lifecycle | Concept & Business Case to Post-EOL Support |
| Power and compound lifecycle | Concept & Business Case to Post-EOL Support |
| Fab build lifecycle | Opportunity & Market Sensing to Post-EOL Support |
| MEMS and sensors lifecycle | Concept & Business Case to Post-EOL Support |
| RF lifecycle | Concept & Business Case to Post-EOL Support |
| Package technology lifecycle | Opportunity & Market Sensing to Post-EOL Support |
| Security lifecycle | Concept & Business Case to Post-EOL Support |
| Equipment lifecycle | Opportunity & Market Sensing to Post-EOL Support |
| Medical lifecycle | Definition & Planning to Post-EOL Support |
| Avionics lifecycle | Definition & Planning to Post-EOL Support |
| Industrial lifecycle | Definition & Planning to Post-EOL Support |
| Automotive SPICE lifecycle | Opportunity & Market Sensing to Maturity & Sustaining |
| Vehicle cybersecurity lifecycle | Opportunity & Market Sensing to Post-EOL Support |
| APQP lifecycle | Concept & Business Case to Post-EOL Support |
| QMS lifecycle | Opportunity & Market Sensing to Decline |
| System lifecycle | Definition & Planning to Post-EOL Support |
| Platform lifecycle | Opportunity & Market Sensing to Post-EOL Support |
| FPGA chip lifecycle | Concept & Business Case to End of Life |
| Structured ASIC lifecycle | Concept & Business Case to End of Life |
| PLC | Opportunity & Market Sensing to Post-EOL Support |
| PDLC | Definition & Planning to Development |
| NPI | Development to Launch |
| Qualification | Validation & Characterisation to Qualification & Production Readiness |
| Yield ramp | Validation & Characterisation to Maturity & Sustaining |
| Obsolescence | Maturity & Sustaining to Post-EOL Support |
- Product lifecycle →The business lifecycle of a semiconductor product, from the first sign of a market opportunity through concept, definition, development, validation, sampling, qualification, launch, ramp, maturity and decline to end of life and the support that continues after the last shipment. The engineering lifecycles run inside it.13 stages, 31 gates, 11 disciplines
- Soft IP lifecycle →One reusable block delivered as synthesisable design code (soft IP), made in-house or taken in from a supplier, from its specification through design, verification, implementation views and quality checks to a versioned release for SoC teams.8 stages, 10 gates, 12 disciplines
- SoC and full-chip lifecycle →The whole chip, from its specification through IP integration, full-chip design and verification, tape-out, bring-up and qualification to production and end of life.15 stages, 22 gates, 17 disciplines
See the product, SoC and Soft IP charts in full
The product lifecycle at a glance
The top row is the product's status, from Concept to Obsolete, each closed by its milestone. Below it, each row is a business discipline and each block names its work in that stage. Select a stage, a gate, a discipline or a block to go to its page. Small lettered markers show where AI is changing the work: red D for a disruption, blue A for an augmentation, green O for an opportunity.
Stage
Business milestones
OAOpportunity acceptedMRMarket requirements approvedCAConcept approvalRQProduct requirements approvedPAPlan approval and development commitCSCustomer samplesDWDesign-in reviewCQCustomer qualification approvedPRProduction releasePRCPricing approvedLRRLaunch readinessLRLaunch reviewFPOFirst production orderVRVolume rampPCNProduct change noticeLCRLifecycle reviewNRNDNot recommended for new designsDDDiscontinuance decisionDNDiscontinuance noticeLTBLast-time buyEOSEnd of support
Engineering and operations milestones
KeyConceptDevelopmentSamplingProductionDiscontinuedObsoleteFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps meanWhat the codes mean
Show this chart as a list
Stages
Product status
- Concept: Opportunity & Market Sensing to Concept & Business Case, ends at Concept approval
- Development: Definition & Planning to Development, ends at Design release
- Sampling: Validation & Characterisation to Qualification & Production Readiness, ends at Production release
- Production: Launch to Decline, ends at Discontinuance decision
- Discontinued: End of Life, ends at Last-time ship
- Obsolete: Post-EOL Support
Business milestones
- Opportunity accepted (OA)
- Market requirements approved (MR)
- Concept approval (CA)
- Product requirements approved (RQ)
- Plan approval and development commit (PA)
- Customer samples (CS)
- Design-in review (DW)
- Customer qualification approved (CQ)
- Production release (PR)
- Pricing approved (PRC)
- Launch readiness (LRR)
- Launch review (LR)
- First production order (FPO)
- Volume ramp (VR)
- Product change notice (PCN)
- Lifecycle review (LCR)
- Not recommended for new designs (NRND)
- Discontinuance decision (DD)
- Discontinuance notice (DN)
- Last-time buy (LTB)
- End of support (EOS)
Engineering and operations milestones
Disciplines
- Product marketing
- Opportunity & Market Sensing: Market sensing (Concept). Market need, target segments and market requirements set out for the concept and the plan.
- Concept & Business Case: Market requirements (Concept). Market need, target segments and market requirements set out for the concept and the plan.
- Definition & Planning: Positioning input (Development). Positioning and messaging drafted from the approved plan while the design is built.
- Development: Messaging draft (Development). Positioning and messaging drafted from the approved plan while the design is built.
- Validation & Characterisation: Product brief (Sampling). Positioning tested with lead customers on samples and launch preparation under way.
- Customer Sampling & Design-in: Message testing (Sampling). Positioning tested with lead customers on samples and launch preparation under way.
- Qualification & Production Readiness: Launch planning (Sampling). Positioning tested with lead customers on samples and launch preparation under way.
- Launch: Product launch (Production). Product launched and its message kept current against competitors.
- Ramp & Growth: Demand generation (Production). Product launched and its message kept current against competitors.
- Maturity & Sustaining: Competitor watch (Production). Product launched and its message kept current against competitors.
- Decline: Successor steering (Production). Product launched and its message kept current against competitors.
- End of Life: Migration messaging (Discontinued). Customers steered to the replacement or migration path once discontinuance is decided.
- Product management
- Concept & Business Case: Business case (Concept). Business case, product requirements and plan approved for development.
- Definition & Planning: Product requirements (Development). Product requirements held under change control while the design is completed and released.
- Development: Requirements control (Development). Product requirements held under change control while the design is completed and released.
- Validation & Characterisation: Sample plan (Sampling). Sample plan run and requirements compliance shown against lead customer feedback.
- Customer Sampling & Design-in: Customer samples (Sampling). Sample plan run and requirements compliance shown against lead customer feedback.
- Qualification & Production Readiness: Production release (Sampling). Sample plan run and requirements compliance shown against lead customer feedback.
- Launch: Launch approval (Production). Product released for volume orders and its line managed through lifecycle reviews.
- Ramp & Growth: Allocation priorities (Production). Product released for volume orders and its line managed through lifecycle reviews.
- Maturity & Sustaining: Lifecycle reviews (Production). Product released for volume orders and its line managed through lifecycle reviews.
- Decline: Phase-down decisions (Production). Product released for volume orders and its line managed through lifecycle reviews.
- End of Life: Discontinuance notice (Discontinued). Discontinuance decided, with the migration path and the customer notice prepared.
- Post-EOL Support: Closing obligations (Obsolete). Notice issued and the product's remaining obligations closed to the end of support.
- Program management
- Concept & Business Case: Definition plan (Concept). Development plan and schedule baselined across the business and engineering.
- Definition & Planning: Integrated schedule (Development). Design release coordinated with the sign-off of every engineering lifecycle.; Schedule baselined (milestone for one item)
- Development: Tape-out and release (Development). Design release coordinated with the sign-off of every engineering lifecycle.
- Validation & Characterisation: Bring-up tracking (Sampling). Sampling, qualification and production readiness coordinated to the plan.
- Customer Sampling & Design-in: Sample tracking (Sampling). Sampling, qualification and production readiness coordinated to the plan.
- Qualification & Production Readiness: Production readiness (Sampling). Sampling, qualification and production readiness coordinated to the plan.
- Launch: Launch coordination (Production). Production release and ramp coordinated, then changes tracked through maturity.
- Ramp & Growth: Ramp coordination (Production). Production release and ramp coordinated, then changes tracked through maturity.
- Maturity & Sustaining: Change tracking (Production). Production release and ramp coordinated, then changes tracked through maturity.
- Decline: Discontinuance planning (Production). Production release and ramp coordinated, then changes tracked through maturity.
- End of Life: Final shipment tracking (Discontinued). Discontinuance programme planned across sales, supply, quality and support.
- Post-EOL Support: Product closure (Obsolete). Final shipments tracked and the product closed with its closure report.
- Business development and sales
- Opportunity & Market Sensing: Customer discovery (Concept). Customer needs gathered and a first lead customer list drawn up.
- Concept & Business Case: Lead customer list (Concept). Customer needs gathered and a first lead customer list drawn up.
- Definition & Planning: Lead customers (Development). Lead customers engaged on the plan and lined up for samples.
- Development: Lead customers lined up (Development). Lead customers engaged on the plan and lined up for samples.
- Validation & Characterisation: Sample placement (Sampling). Samples placed with lead customers and design-ins pursued into a pipeline.
- Customer Sampling & Design-in: Design-in pursuit (Sampling). Samples placed with lead customers and design-ins pursued into a pipeline.; First design wins (milestone for one item)
- Qualification & Production Readiness: Design win follow-up (Sampling). Samples placed with lead customers and design-ins pursued into a pipeline.
- Launch: Quotes and forecast (Production). Design wins converted to orders and accounts managed through the product's life.
- Ramp & Growth: Production orders (Production). Design wins converted to orders and accounts managed through the product's life.
- Maturity & Sustaining: Account management (Production). Design wins converted to orders and accounts managed through the product's life.
- Decline: Customer base review (Production). Design wins converted to orders and accounts managed through the product's life.
- End of Life: Last-time-buy orders (Discontinued). Customers told of the discontinuance, their last-time-buy orders confirmed and remaining accounts moved to a successor.
- Field applications
- Definition & Planning: Customer use cases (Development). Customer use cases written for the product requirements, then evaluation hardware and reference designs planned while the design is built.
- Development: Evaluation kit plan (Development). Customer use cases written for the product requirements, then evaluation hardware and reference designs planned while the design is built.
- Validation & Characterisation: Evaluation kit (Sampling). Evaluation kits and reference designs supporting customer design-ins.; Evaluation kit ready (milestone for one item)
- Customer Sampling & Design-in: Design-in support (Sampling). Evaluation kits and reference designs supporting customer design-ins.
- Qualification & Production Readiness: Application notes (Sampling). Evaluation kits and reference designs supporting customer design-ins.
- Launch: Training and content (Production). Application notes released and customers supported in production.
- Ramp & Growth: Production support (Production). Application notes released and customers supported in production.
- Maturity & Sustaining: Field support (Production). Application notes released and customers supported in production.
- Decline: Migration planning (Production). Application notes released and customers supported in production.
- End of Life: Customer migration (Discontinued). Customer migration to the replacement planned and customers supported through it to the last shipment.
- Quality and reliability
- Concept & Business Case: First quality targets (Concept). Quality and reliability targets set for the intended markets.
- Definition & Planning: Reliability targets (Development). Qualification plan drafted against the released design.
- Development: Qualification planning (Development). Qualification plan drafted against the released design.
- Validation & Characterisation: Early reliability (Sampling). Qualification plan approved and parts from the production flow entering qualification.
- Customer Sampling & Design-in: Qualification plan (Sampling). Qualification plan approved and parts from the production flow entering qualification.
- Qualification & Production Readiness: Qualification testing (Sampling). Qualification plan approved and parts from the production flow entering qualification.
- Launch: Control plans (Production). Qualification passed, then field quality and change notices managed in production.
- Ramp & Growth: Early field quality (Production). Qualification passed, then field quality and change notices managed in production.
- Maturity & Sustaining: Change notification (Production). Qualification passed, then field quality and change notices managed in production.
- Decline: Field quality watch (Production). Qualification passed, then field quality and change notices managed in production.
- End of Life: Quality archive (Discontinued). Change notices and field quality kept up while the discontinuance runs.
- Post-EOL Support: Warranty and returns (Obsolete). Warranty, failure analysis and the product archive closed out to the end of support.
- Supply chain and operations
- Definition & Planning: Supplier selection (Development). Suppliers selected and the supply chain plan made final, with suppliers ready to build at the design release.
- Development: Supplier readiness (Development). Suppliers selected and the supply chain plan made final, with suppliers ready to build at the design release.
- Validation & Characterisation: Sample builds (Sampling). Demand forecast drawn from lead customers and production readiness prepared.
- Customer Sampling & Design-in: Demand forecast draft (Sampling). Demand forecast drawn from lead customers and production readiness prepared.
- Qualification & Production Readiness: Qualification lots (Sampling). Demand forecast drawn from lead customers and production readiness prepared.; Supply ready (milestone for one item)
- Launch: Capacity booking (Production). Supply readiness shown, capacity ramped and deliveries run to the forecast.
- Ramp & Growth: Capacity ramp (Production). Supply readiness shown, capacity ramped and deliveries run to the forecast.
- Maturity & Sustaining: Supply and delivery (Production). Supply readiness shown, capacity ramped and deliveries run to the forecast.
- Decline: Supply risk watch (Production). Supply readiness shown, capacity ramped and deliveries run to the forecast.
- End of Life: Final builds (Discontinued). Supply risks assessed and the final inventory and supply plan agreed.
- Post-EOL Support: Aftermarket supply (Obsolete). Final builds shipped and aftermarket supply arranged.
- Finance
- Concept & Business Case: Financial model (Concept). Financial model and cost and price targets set for the plan.
- Definition & Planning: Cost and price targets (Development). Development budget tracked against the plan.
- Development: Budget tracking (Development). Development budget tracked against the plan.
- Validation & Characterisation: Product cost tracking (Sampling). Budget and product cost tracked through sampling and qualification.
- Customer Sampling & Design-in: Quote pricing (Sampling). Budget and product cost tracked through sampling and qualification.
- Qualification & Production Readiness: Standard cost (Sampling). Budget and product cost tracked through sampling and qualification.
- Launch: Price approval (Production). Prices published and revenue and margin reported in production.
- Ramp & Growth: Revenue tracking (Production). Prices published and revenue and margin reported in production.
- Maturity & Sustaining: Margin review (Production). Prices published and revenue and margin reported in production.
- Decline: Discontinuance impact (Production). Prices published and revenue and margin reported in production.
- End of Life: End-of-life costs (Discontinued). Financial impact of the discontinuance assessed.
- Post-EOL Support: Reserves review (Obsolete). Inventory and reserves reviewed after the last shipment.
- Legal and compliance
- Definition & Planning: Licence negotiation (Development). Licence, partner and freedom to operate reviews done, agreements signed and export classification started.
- Development: Agreements signed (Development). Licence, partner and freedom to operate reviews done, agreements signed and export classification started.
- Validation & Characterisation: Export classification (Sampling). Sample agreements and export classification in place for sample shipments.; Export classification (milestone for one item)
- Customer Sampling & Design-in: Sample agreements (Sampling). Sample agreements and export classification in place for sample shipments.
- Qualification & Production Readiness: Compliance declarations (Sampling). Sample agreements and export classification in place for sample shipments.
- Launch: Terms of sale (Production). Compliance declarations and terms of sale released and kept current.
- Ramp & Growth: Contract support (Production). Compliance declarations and terms of sale released and kept current.
- Maturity & Sustaining: Licence compliance (Production). Compliance declarations and terms of sale released and kept current.
- Decline: Notice review (Production). Compliance declarations and terms of sale released and kept current.
- End of Life: Discontinuance terms (Discontinued). Discontinuance notice and contract terms reviewed.
- Post-EOL Support: Record retention (Obsolete). Record retention arranged to the end of support.
- Customer support
- Customer Sampling & Design-in: Knowledge base (Sampling). Support knowledge base started from lead customer feedback.
- Qualification & Production Readiness: Support readiness (Sampling). Support knowledge base started from lead customer feedback.
- Launch: Support switch-on (Production). Support processes live and escalations handled in production.; Support live (milestone for one item)
- Ramp & Growth: Escalations and orders (Production). Support processes live and escalations handled in production.
- Maturity & Sustaining: Customer support (Production). Support processes live and escalations handled in production.
- Decline: Migration questions (Production). Support processes live and escalations handled in production.
- End of Life: Discontinuance queries (Discontinued). Customer questions on the discontinuance handled.
- Post-EOL Support: Warranty support (Obsolete). Support and warranty run after the last shipment, then closed.
- Engineering leadership
- Opportunity & Market Sensing: Technology scan (Concept). Technical feasibility shown and engineering resources committed.
- Concept & Business Case: Feasibility view (Concept). Technical feasibility shown and engineering resources committed.
- Definition & Planning: Specification freeze (Development). Every engineering lifecycle signed off and the design released.
- Development: Tape-out and release (Development). Every engineering lifecycle signed off and the design released.; Engineering sign-off (milestone for one item)
- Validation & Characterisation: Bring-up and validation (Sampling). Silicon and system validated, with errata documented for the samples.
- Customer Sampling & Design-in: Errata and fixes (Sampling). Silicon and system validated, with errata documented for the samples.
- Qualification & Production Readiness: Production test release (Sampling). Silicon and system validated, with errata documented for the samples.
- Launch: Yield learning (Production). Production test and characterisation released, then sustaining engineering.
- Ramp & Growth: Ramp yield fixes (Production). Production test and characterisation released, then sustaining engineering.
- Maturity & Sustaining: Cost reduction (Production). Production test and characterisation released, then sustaining engineering.
- Decline: Sustaining engineering (Production). Production test and characterisation released, then sustaining engineering.
- End of Life: Design data archive (Discontinued). Design and test data gathered and archived by the last shipment as the product is discontinued.
Where every engineering lifecycle fits inside it, stage by stage
The SoC lifecycle at a glance
Each row is a discipline. A shaded block shows the stages it works in and how mature its work is by the end of each one. Select a stage, a gate, a discipline or a block to go to its page. Small lettered markers show where AI is changing the work: red D for a disruption, blue A for an augmentation, green O for an opportunity.
Stage
Product milestones
Chip milestones
TFTR1, technical readiness reviewTR1: Technology feasibilitySFSpecification freezeIICIP integration completeRFRTL freezeVSVerification sign-offDSDFT insertion sign-offPSPhysical sign-offTTRTR2, technical readiness reviewTR2: Tape-out technology readinessTOTape-outFSFirst siliconFPTFirst packaged parts testedSVSilicon validatedQSQualification startQPTR3, technical readiness reviewQualification passedDADesign and test data archived
Key0.0Started0.3Early draft0.5In progress0.8Feature complete1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.AI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps meanWhat the codes mean
Show this chart as a list
Stages
- Concept & Feasibility
- SoC Specification & Architecture
- IP Integration
- SoC RTL Design
- Full-Chip Verification
- Full-Chip DFT
- Physical Design & Sign-off
- Tape-out
- Foundry & Mask
- Packaging & Test
- Bring-up & Silicon Validation
- Qualification & Reliability
- Production Ramp & Yield
- Volume Production & Sustaining
- End of Life
Product milestones
Chip milestones
- TR1: Technology feasibility (TF) (technical readiness review TR1)
- Specification freeze (SF)
- IP integration complete (IIC)
- RTL freeze (RF)
- Verification sign-off (VS)
- DFT insertion sign-off (DS)
- Physical sign-off (PS)
- TR2: Tape-out technology readiness (TTR) (technical readiness review TR2)
- Tape-out (TO)
- First silicon (FS)
- First packaged parts tested (FPT)
- Silicon validated (SV)
- Qualification start (QS)
- Qualification passed (QP) (technical readiness review TR3)
- Design and test data archived (DA)
Disciplines
- SoC architecture and specification
- Concept & Feasibility: maturity 0.0, Started. Requirements and candidate architectures written down; feasibility of the chosen one shown at the technical readiness review.
- SoC Specification & Architecture: maturity 0.3, Early draft. Architecture specification frozen and baselined with the product plan; later changes go through change control.; Architecture freeze (milestone for one item)
- IP Integration: maturity 0.5, In progress. Specification clarified as IP blocks are integrated, with every change controlled.
- SoC RTL Design: maturity 0.8, Feature complete. Specification matches the frozen RTL; only clarifications remain.
- Full-Chip Verification: maturity 1.0, Complete. Specification confirmed against the verified chip.
- System modelling and virtual prototyping
- Concept & Feasibility: maturity 0.0, Started. First architecture model running the main use cases for the feasibility review.
- SoC Specification & Architecture: maturity 0.3, Early draft. Architecture model final for the specification; first virtual platform available to software teams.; Virtual platform available (milestone for one item)
- IP Integration: maturity 0.5, In progress. Virtual platform updated with the integrated IP models.
- SoC RTL Design: maturity 0.8, Feature complete. Virtual platform matches the frozen RTL.
- Full-Chip Verification: maturity 1.0, Complete. Reference models final and correlated with the verified RTL.
- Full-Chip DFT: maturity Freeze, Frozen. Models locked to the verified design; the virtual platform supports software until silicon is validated.
- Physical Design & Sign-off: maturity Freeze, Frozen. Models locked to the verified design; the virtual platform supports software until silicon is validated.
- Tape-out: maturity Freeze, Frozen. Models locked to the verified design; the virtual platform supports software until silicon is validated.
- Foundry & Mask: maturity Freeze, Frozen. Models locked to the verified design; the virtual platform supports software until silicon is validated.
- Packaging & Test: maturity Freeze, Frozen. Models locked to the verified design; the virtual platform supports software until silicon is validated.
- Bring-up & Silicon Validation: maturity Freeze, Frozen. Models locked to the verified design; the virtual platform supports software until silicon is validated.
- Performance and power analysis
- Concept & Feasibility: maturity 0.0, Started. Performance and power targets drafted from the architecture model.
- SoC Specification & Architecture: maturity 0.3, Early draft. Targets agreed and frozen with the specification.
- IP Integration: maturity 0.5, In progress. Targets tracked on the integrated RTL, with gaps fed back to design.
- SoC RTL Design: maturity 0.8, Feature complete. Performance measured on the frozen RTL and on emulation; the report is final for verification sign-off.
- Full-Chip Verification: maturity 0.8, Feature complete. Performance measured on the frozen RTL and on emulation; the report is final for verification sign-off.
- Full-Chip DFT: maturity 1.0, Complete. Performance and power targets met, with power confirmed on the signed-off design; after silicon, the results are correlated with measurements.
- Physical Design & Sign-off: maturity 1.0, Complete. Performance and power targets met, with power confirmed on the signed-off design; after silicon, the results are correlated with measurements.; Performance and power targets met
- Tape-out: maturity 1.0, Complete. Performance and power targets met, with power confirmed on the signed-off design; after silicon, the results are correlated with measurements.
- Foundry & Mask: maturity 1.0, Complete. Performance and power targets met, with power confirmed on the signed-off design; after silicon, the results are correlated with measurements.
- Packaging & Test: maturity 1.0, Complete. Performance and power targets met, with power confirmed on the signed-off design; after silicon, the results are correlated with measurements.
- Bring-up & Silicon Validation: maturity 1.0, Complete. Performance and power targets met, with power confirmed on the signed-off design; after silicon, the results are correlated with measurements.; Silicon correlation complete
- IP integration
- Concept & Feasibility: maturity 0.0, Started. First list of the IP blocks needed, with their source and silicon status.
- SoC Specification & Architecture: maturity 0.3, Early draft. IP selection list final, every block with a source and a version plan.
- IP Integration: maturity 0.5, In progress. Early IP releases connected and connectivity checked.
- SoC RTL Design: maturity 0.8, Feature complete. Final IP releases integrated and versions locked for the RTL freeze.; IP versions locked (milestone for one item)
- Full-Chip Verification: maturity 1.0, Complete. Integration verified in full-chip verification and design for test.
- Full-Chip DFT: maturity 1.0, Complete. Integration verified in full-chip verification and design for test.
- Physical Design & Sign-off: maturity Freeze, Frozen. IP versions locked in the taped-out design and recorded for every part.
- Tape-out: maturity Freeze, Frozen. IP versions locked in the taped-out design and recorded for every part.
- Foundry & Mask: maturity Freeze, Frozen. IP versions locked in the taped-out design and recorded for every part.
- Packaging & Test: maturity Freeze, Frozen. IP versions locked in the taped-out design and recorded for every part.
- Bring-up & Silicon Validation: maturity Freeze, Frozen. IP versions locked in the taped-out design and recorded for every part.
- SoC RTL design
- Concept & Feasibility: maturity 0.0, Started. The chip's own blocks and glue logic listed, with design reuse, coding approach and a gate count and effort estimate agreed with the architects; no code yet.
- SoC Specification & Architecture: maturity 0.3, Early draft. Micro-architecture specified for each block, ready for coding.
- IP Integration: maturity 0.5, In progress. Main features coded and running in simulation on the integrated IP.
- SoC RTL Design: maturity 0.8, Feature complete. Every feature coded and lint clean; features frozen at the RTL freeze.; RTL freeze (milestone for one item)
- Full-Chip Verification: maturity 1.0, Complete. RTL verified and released; only reviewed fixes and engineering change orders go in.
- Full-Chip DFT: maturity 1.0, Complete. RTL verified and released; only reviewed fixes and engineering change orders go in.
- Physical Design & Sign-off: maturity Freeze, Frozen. RTL locked in the taped-out design; silicon fixes go into a new version.
- Tape-out: maturity Freeze, Frozen. RTL locked in the taped-out design; silicon fixes go into a new version.
- Foundry & Mask: maturity Freeze, Frozen. RTL locked in the taped-out design; silicon fixes go into a new version.
- Packaging & Test: maturity Freeze, Frozen. RTL locked in the taped-out design; silicon fixes go into a new version.
- Bring-up & Silicon Validation: maturity Freeze, Frozen. RTL locked in the taped-out design; silicon fixes go into a new version.
- Full-chip verification
- Concept & Feasibility: maturity 0.0, Started. Verification approach agreed with the architects: which IP environments are reused, where simulation, formal and emulation are used, and an effort and compute estimate; no plan or testbench yet.
- SoC Specification & Architecture: maturity 0.3, Early draft. Environment: verification plan drafted from the frozen specification; testbench architecture, verification IP and coverage model planned.
- IP Integration: maturity 0.5, In progress. Environment: testbench, verification IP and checkers running on the integrated RTL, with coverage collection started.
- SoC RTL Design: maturity 0.8, Feature complete. Environment complete at the RTL freeze. Results: regressions and coverage closure under way on the frozen RTL, with bugs going back to design.
- Full-Chip Verification: maturity 1.0, Complete. Results: coverage closed and open bugs fixed or waived; gate-level checks run on the netlist.; Coverage closure
- Full-Chip DFT: maturity 1.0, Complete. Results: coverage closed and open bugs fixed or waived; gate-level checks run on the netlist.
- Physical Design & Sign-off: maturity Freeze, Frozen. Results locked with the taped-out design; silicon escapes reviewed against them.
- Tape-out: maturity Freeze, Frozen. Results locked with the taped-out design; silicon escapes reviewed against them.
- Foundry & Mask: maturity Freeze, Frozen. Results locked with the taped-out design; silicon escapes reviewed against them.
- Packaging & Test: maturity Freeze, Frozen. Results locked with the taped-out design; silicon escapes reviewed against them.
- Bring-up & Silicon Validation: maturity Freeze, Frozen. Results locked with the taped-out design; silicon escapes reviewed against them.
- Emulation
- SoC Specification & Architecture: maturity 0.0, Started. Emulation scope agreed with verification and software from the design size in the specification: the tests and software to run, the emulator capacity to book and the first RTL drop to build; no model built yet.
- IP Integration: maturity 0.3, Early draft. Emulation model built from the integrated RTL.
- SoC RTL Design: maturity 0.5, In progress. Emulation platform running the frozen RTL.
- Full-Chip Verification: maturity 0.8, Feature complete. Software and long tests running on emulation; the platform is final for verification sign-off.; First OS boot on emulation
- Full-Chip DFT: maturity 1.0, Complete. Final regressions run on the netlist before tape-out.
- Physical Design & Sign-off: maturity 1.0, Complete. Final regressions run on the netlist before tape-out.
- Tape-out: maturity 1.0, Complete. Final regressions run on the netlist before tape-out.
- Foundry & Mask: maturity Freeze, Frozen. Platform locked to the taped-out design and used to debug silicon.
- Packaging & Test: maturity Freeze, Frozen. Platform locked to the taped-out design and used to debug silicon.
- Bring-up & Silicon Validation: maturity Freeze, Frozen. Platform locked to the taped-out design and used to debug silicon.
- FPGA prototyping
- SoC Specification & Architecture: maturity 0.0, Started. Prototype need agreed with software and validation, with the board platform options and the number of devices estimated from the design size in the specification; no partitioning yet.
- IP Integration: maturity 0.3, Early draft. Board chosen and the design partitioned across devices.
- SoC RTL Design: maturity 0.5, In progress. First prototype running the frozen RTL.
- Full-Chip Verification: maturity 0.8, Feature complete. Prototype final at verification sign-off, running drivers and software at speed.; Prototype available for software
- Full-Chip DFT: maturity 1.0, Complete. Prototype complete on the verified design; kept running for software enablement and silicon validation until the silicon is validated.
- Physical Design & Sign-off: maturity 1.0, Complete. Prototype complete on the verified design; kept running for software enablement and silicon validation until the silicon is validated.
- Tape-out: maturity 1.0, Complete. Prototype complete on the verified design; kept running for software enablement and silicon validation until the silicon is validated.
- Foundry & Mask: maturity 1.0, Complete. Prototype complete on the verified design; kept running for software enablement and silicon validation until the silicon is validated.
- Packaging & Test: maturity 1.0, Complete. Prototype complete on the verified design; kept running for software enablement and silicon validation until the silicon is validated.
- Bring-up & Silicon Validation: maturity 1.0, Complete. Prototype complete on the verified design; kept running for software enablement and silicon validation until the silicon is validated.
- Full-chip design for test
- SoC Specification & Architecture: maturity 0.0, Started. Test architecture defined against the specification.
- IP Integration: maturity 0.3, Early draft. Test structures planned around each IP block's own.
- SoC RTL Design: maturity 0.5, In progress. Scan and built-in self-test logic inserted in the frozen RTL.
- Full-Chip Verification: maturity 0.8, Feature complete. Patterns generated on the verified netlist, with coverage being closed.
- Full-Chip DFT: maturity 1.0, Complete. Test coverage signed off at the DFT sign-off.
- Physical Design & Sign-off: maturity Freeze, Frozen. Test patterns final at physical sign-off and locked; used to bring up the test program and diagnose failures in volume.; Test patterns final
- Tape-out: maturity Freeze, Frozen. Test patterns final at physical sign-off and locked; used to bring up the test program and diagnose failures in volume.
- Foundry & Mask: maturity Freeze, Frozen. Test patterns final at physical sign-off and locked; used to bring up the test program and diagnose failures in volume.
- Packaging & Test: maturity Freeze, Frozen. Test patterns final at physical sign-off and locked; used to bring up the test program and diagnose failures in volume.
- Bring-up & Silicon Validation: maturity Freeze, Frozen. Test patterns final at physical sign-off and locked; used to bring up the test program and diagnose failures in volume.
- Qualification & Reliability: maturity Freeze, Frozen. Test patterns final at physical sign-off and locked; used to bring up the test program and diagnose failures in volume.
- Production Ramp & Yield: maturity Freeze, Frozen. Test patterns final at physical sign-off and locked; used to bring up the test program and diagnose failures in volume.
- Volume Production & Sustaining: maturity Freeze, Frozen. Test patterns final at physical sign-off and locked; used to bring up the test program and diagnose failures in volume.
- Full-chip physical design
- SoC Specification & Architecture: maturity 0.0, Started. Die size and floorplan estimated for the product plan.
- IP Integration: maturity 0.3, Early draft. Floorplan and power plan outlined on the integrated design.
- SoC RTL Design: maturity 0.5, In progress. Floorplan updated on the frozen RTL with the process design kit.
- Full-Chip Verification: maturity 0.8, Feature complete. Trial layouts closing timing on the verified netlist.
- Full-Chip DFT: maturity 1.0, Complete. Layout complete with the final test patterns inserted.
- Physical Design & Sign-off: maturity Freeze, Frozen. Timing and physical checks signed off and the layout locked; released to the foundry at tape-out.; Timing sign-off
- Tape-out: maturity Freeze, Frozen. Timing and physical checks signed off and the layout locked; released to the foundry at tape-out.
- Firmware and software
- SoC Specification & Architecture: maturity 0.0, Started. Software architecture drafted against the specification.
- IP Integration: maturity 0.3, Early draft. Boot code and drivers being written on the virtual platform.
- SoC RTL Design: maturity 0.5, In progress. Pre-silicon software tests running on the frozen RTL in emulation.
- Full-Chip Verification: maturity 0.8, Feature complete. Boot code and pre-silicon drivers complete; boot code frozen into the masks at physical sign-off.
- Full-Chip DFT: maturity 0.8, Feature complete. Boot code and pre-silicon drivers complete; boot code frozen into the masks at physical sign-off.
- Physical Design & Sign-off: maturity 0.8, Feature complete. Boot code and pre-silicon drivers complete; boot code frozen into the masks at physical sign-off.; Boot code freeze (into the masks) (milestone for one item)
- Tape-out: maturity 0.8, Feature complete. Boot code and pre-silicon drivers complete; boot code frozen into the masks at physical sign-off.
- Foundry & Mask: maturity 0.8, Feature complete. Boot code and pre-silicon drivers complete; boot code frozen into the masks at physical sign-off.
- Packaging & Test: maturity 0.8, Feature complete. Boot code and pre-silicon drivers complete; boot code frozen into the masks at physical sign-off.
- Bring-up & Silicon Validation: maturity 1.0, Complete. Drivers and board support working on silicon; the production software release is made with the production release.
- Qualification & Reliability: maturity 1.0, Complete. Drivers and board support working on silicon; the production software release is made with the production release.
- Production Ramp & Yield: maturity Freeze, Frozen. Released software locked; fixes come in maintenance releases until end of life.
- Volume Production & Sustaining: maturity Freeze, Frozen. Released software locked; fixes come in maintenance releases until end of life.
- End of Life: maturity Freeze, Frozen. Released software locked; fixes come in maintenance releases until end of life.
- Foundry and process
- Concept & Feasibility: maturity 0.0, Started. Process node and options chosen, with technology risks shown feasible.
- SoC Specification & Architecture: maturity 0.3, Early draft. Process options and the design kit version agreed for design.
- IP Integration: maturity 0.5, In progress. Design kit supporting floorplanning and implementation.
- SoC RTL Design: maturity 0.5, In progress. Design kit supporting floorplanning and implementation.
- Full-Chip Verification: maturity 0.8, Feature complete. Design kit and rule decks checked against trial layouts.
- Full-Chip DFT: maturity 0.8, Feature complete. Design kit and rule decks checked against trial layouts.
- Physical Design & Sign-off: maturity 1.0, Complete. Sign-off version of the design kit and rule decks agreed with the foundry.
- Tape-out: maturity Freeze, Frozen. Masks made and the process fixed for this product; later process changes come with a change notice.
- Foundry & Mask: maturity Freeze, Frozen. Masks made and the process fixed for this product; later process changes come with a change notice.; Mask set complete
- Packaging & Test: maturity Freeze, Frozen. Masks made and the process fixed for this product; later process changes come with a change notice.
- Bring-up & Silicon Validation: maturity Freeze, Frozen. Masks made and the process fixed for this product; later process changes come with a change notice.
- Qualification & Reliability: maturity Freeze, Frozen. Masks made and the process fixed for this product; later process changes come with a change notice.
- Production Ramp & Yield: maturity Freeze, Frozen. Masks made and the process fixed for this product; later process changes come with a change notice.
- Volume Production & Sustaining: maturity Freeze, Frozen. Masks made and the process fixed for this product; later process changes come with a change notice.
- Packaging and test
- Concept & Feasibility: maturity 0.0, Started. Package options assessed for power, pins and cost.
- SoC Specification & Architecture: maturity 0.3, Early draft. Package type chosen with the specification.
- IP Integration: maturity 0.5, In progress. Pin-out and bump plan agreed with the floorplan.
- SoC RTL Design: maturity 0.5, In progress. Pin-out and bump plan agreed with the floorplan.
- Full-Chip Verification: maturity 0.8, Feature complete. Package design and test approach checked against the trial layouts.
- Full-Chip DFT: maturity 0.8, Feature complete. Package design and test approach checked against the trial layouts.
- Physical Design & Sign-off: maturity 1.0, Complete. Package design final at physical sign-off; test hardware and test program working on silicon, released for production.
- Tape-out: maturity 1.0, Complete. Package design final at physical sign-off; test hardware and test program working on silicon, released for production.
- Foundry & Mask: maturity 1.0, Complete. Package design final at physical sign-off; test hardware and test program working on silicon, released for production.
- Packaging & Test: maturity 1.0, Complete. Package design final at physical sign-off; test hardware and test program working on silicon, released for production.
- Bring-up & Silicon Validation: maturity 1.0, Complete. Package design final at physical sign-off; test hardware and test program working on silicon, released for production.
- Qualification & Reliability: maturity 1.0, Complete. Package design final at physical sign-off; test hardware and test program working on silicon, released for production.; Test program released
- Production Ramp & Yield: maturity 1.0, Complete. Package design final at physical sign-off; test hardware and test program working on silicon, released for production.
- Volume Production & Sustaining: maturity 1.0, Complete. Package design final at physical sign-off; test hardware and test program working on silicon, released for production.
- Silicon validation
- Full-Chip Verification: maturity 0.0, Started. Validation planning started from the verification plan.
- Full-Chip DFT: maturity 0.3, Early draft. Validation plan drafted with the test structures and debug access.
- Physical Design & Sign-off: maturity 0.5, In progress. Validation plan final at physical sign-off; boards being built.
- Tape-out: maturity 0.5, In progress. Validation plan final at physical sign-off; boards being built.
- Foundry & Mask: maturity 0.8, Feature complete. Boards and lab ready for first silicon.
- Packaging & Test: maturity 0.8, Feature complete. Boards and lab ready for first silicon.
- Bring-up & Silicon Validation: maturity 1.0, Complete. Silicon brought up and measured against the specification, with errata listed and kept up to date.; Validation sign-off
- Qualification & Reliability: maturity 1.0, Complete. Silicon brought up and measured against the specification, with errata listed and kept up to date.
- Production Ramp & Yield: maturity 1.0, Complete. Silicon brought up and measured against the specification, with errata listed and kept up to date.
- Volume Production & Sustaining: maturity 1.0, Complete. Silicon brought up and measured against the specification, with errata listed and kept up to date.
- End of Life: maturity 1.0, Complete. Silicon brought up and measured against the specification, with errata listed and kept up to date.
- Quality and reliability
- SoC Specification & Architecture: maturity 0.0, Started. Reliability requirements set from the specification and the target market.
- IP Integration: maturity 0.3, Early draft. Design for reliability reviewed as the design is integrated and coded.
- SoC RTL Design: maturity 0.3, Early draft. Design for reliability reviewed as the design is integrated and coded.
- Full-Chip Verification: maturity 0.5, In progress. Reliability checks run on the design ahead of sign-off.
- Full-Chip DFT: maturity 0.5, In progress. Reliability checks run on the design ahead of sign-off.
- Physical Design & Sign-off: maturity 0.5, In progress. Reliability checks run on the design ahead of sign-off.
- Tape-out: maturity 0.8, Feature complete. Qualification plan final for first silicon.
- Foundry & Mask: maturity 0.8, Feature complete. Qualification plan final for first silicon.
- Packaging & Test: maturity 0.8, Feature complete. Qualification plan final for first silicon.
- Bring-up & Silicon Validation: maturity 0.8, Feature complete. Qualification plan final for first silicon.
- Qualification & Reliability: maturity 1.0, Complete. Qualification passed on parts from the production flow; field quality monitored to end of life.; Qualification pass
- Production Ramp & Yield: maturity 1.0, Complete. Qualification passed on parts from the production flow; field quality monitored to end of life.
- Volume Production & Sustaining: maturity 1.0, Complete. Qualification passed on parts from the production flow; field quality monitored to end of life.
- End of Life: maturity 1.0, Complete. Qualification passed on parts from the production flow; field quality monitored to end of life.
- Manufacturing and yield
- Foundry & Mask: maturity 0.0, Started. Wafer start plan drafted for first silicon.
- Packaging & Test: maturity 0.3, Early draft. Yield learning started on the first lots.
- Bring-up & Silicon Validation: maturity 0.5, In progress. Yield improving on engineering lots.
- Qualification & Reliability: maturity 0.8, Feature complete. Ramp plan ready for the production release.
- Production Ramp & Yield: maturity 1.0, Complete. Yield target met and volume supply running to the last builds.; Yield target met
- Volume Production & Sustaining: maturity 1.0, Complete. Yield target met and volume supply running to the last builds.
- End of Life: maturity 1.0, Complete. Yield target met and volume supply running to the last builds.
- Product management
- Concept & Feasibility: maturity 0.0, Started. Business case approved and a team funded to define the product.
- SoC Specification & Architecture: maturity 0.3, Early draft. Product plan agreed: market, cost, schedule and feature set.
- IP Integration: maturity 0.3, Early draft. Product plan agreed: market, cost, schedule and feature set.
- SoC RTL Design: maturity 0.3, Early draft. Product plan agreed: market, cost, schedule and feature set.
- Full-Chip Verification: maturity 0.5, In progress. Customer engagement and sampling plans prepared while the design closes.
- Full-Chip DFT: maturity 0.5, In progress. Customer engagement and sampling plans prepared while the design closes.
- Physical Design & Sign-off: maturity 0.5, In progress. Customer engagement and sampling plans prepared while the design closes.
- Tape-out: maturity 0.8, Feature complete. Design released to the foundry; samples and design wins being prepared.
- Foundry & Mask: maturity 0.8, Feature complete. Design released to the foundry; samples and design wins being prepared.
- Packaging & Test: maturity 0.8, Feature complete. Design released to the foundry; samples and design wins being prepared.
- Bring-up & Silicon Validation: maturity 0.8, Feature complete. Design released to the foundry; samples and design wins being prepared.
- Qualification & Reliability: maturity 1.0, Complete. Product released for volume; supply, forecasts and the product's life managed to its end.
- Production Ramp & Yield: maturity 1.0, Complete. Product released for volume; supply, forecasts and the product's life managed to its end.; Ramp complete (Product lifecycle) (milestone for one item)
- Volume Production & Sustaining: maturity 1.0, Complete. Product released for volume; supply, forecasts and the product's life managed to its end.; Lifecycle review (Product lifecycle) (milestone for one item)
- End of Life: maturity 1.0, Complete. Product released for volume; supply, forecasts and the product's life managed to its end.; End-of-life notice
The Soft IP lifecycle at a glance
Each row is a discipline. A shaded block shows the stages it works in and how mature its work is by the end of each one. Select a stage, a gate, a discipline or a block to go to its page. Small lettered markers show where AI is changing the work: red D for a disruption, blue A for an augmentation, green O for an opportunity.
Stage
IP product milestones
IP engineering milestones
Key0.0Specified0.3Pre-alpha0.5Alpha0.8Beta1.0ReleasedLockedFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.AI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps meanWhat the codes mean
Show this chart as a list
Stages
IP product milestones
IP engineering milestones
- TR1: Technology feasibility (TF) (technical readiness review TR1)
- IP specification freeze (ISF)
- Micro-architecture review (IMR)
- Early access release (EA)
- IP RTL freeze (IRF)
- IP verification sign-off (IVS) (technical readiness review TR2)
- IP views complete (IVC)
- IP quality sign-off (IQS)
- IP release (IR)
Disciplines
- IP architecture
- IP Specification & Architecture: maturity 0.0, Specified. Requirements gathered and the specification written down, with interfaces and configuration options.
- Micro-architecture: maturity 0.3, Pre-alpha. Specification clarified against the micro-architecture, with open questions tracked.
- RTL to Early Access: maturity 0.5, Alpha. Specification stable while the main features are coded; changes go through change control.
- RTL Completion: maturity 0.8, Beta. Specification matches the feature-complete RTL; only clarifications remain.
- IP Verification: maturity 1.0, Released. Specification confirmed against the verified block.
- IP system modelling
- IP Specification & Architecture: maturity 0.0, Specified. Model scope agreed with the SoC virtual platform teams.
- Micro-architecture: maturity 0.3, Pre-alpha. Model outlined from the micro-architecture, with the main transactions running.
- RTL to Early Access: maturity 0.5, Alpha. Model released to SoC teams with the early access drop.; IP model available
- RTL Completion: maturity 0.8, Beta. Model updated to match the feature-complete RTL.
- IP Verification: maturity 1.0, Released. Model correlated with the verified RTL.
- IP DFT & Implementation Views: maturity 1.0, Released. Model correlated with the verified RTL.
- IP Quality Checks: maturity 1.0, Released. Model correlated with the verified RTL.
- IP Release & Hand-off: maturity Locked. Model locked and released with this version of the block.
- IP performance analysis
- IP Specification & Architecture: maturity 0.0, Specified. Throughput, latency and power targets set with the integrators.
- Micro-architecture: maturity 0.3, Pre-alpha. Targets checked against the micro-architecture on the model and tracked on early RTL drops.
- RTL to Early Access: maturity 0.3, Pre-alpha. Targets checked against the micro-architecture on the model and tracked on early RTL drops.
- RTL Completion: maturity 0.5, Alpha. Targets tracked on the feature-complete RTL; gaps fed back to design.
- IP Verification: maturity 0.8, Beta. Performance measured on the frozen RTL; the report is final for verification sign-off.
- IP DFT & Implementation Views: maturity 1.0, Released. Performance and power confirmed, with power estimated from the reference synthesis.; Performance and power targets met
- IP RTL design
- IP Specification & Architecture: maturity 0.0, Specified. Design approach outlined against the specification.
- Micro-architecture: maturity 0.3, Pre-alpha. Micro-architecture reviewed: structure, clocking, registers and configuration logic.
- RTL to Early Access: maturity 0.5, Alpha. Main features coded and running in simulation; the early access drop is built from it.
- RTL Completion: maturity 0.8, Beta. Every feature and configuration option coded, lint and clock domain crossing checks clean; features frozen.; IP RTL freeze (milestone for one item)
- IP Verification: maturity 1.0, Released. RTL verified and released; only reviewed bug fixes went in after the freeze.
- IP DFT & Implementation Views: maturity 1.0, Released. RTL verified and released; only reviewed bug fixes went in after the freeze.
- IP Quality Checks: maturity 1.0, Released. RTL verified and released; only reviewed bug fixes went in after the freeze.
- IP Release & Hand-off: maturity Locked. RTL locked with the release; fixes come in a new version.
- IP verification
- IP Specification & Architecture: maturity 0.0, Specified. Environment: the verification approach agreed from the specification: what to check, how, and in which configurations.
- Micro-architecture: maturity 0.3, Pre-alpha. Environment: verification plan approved at the micro-architecture review; testbench, verification IP, checkers and coverage model being built from the specification.
- RTL to Early Access: maturity 0.5, Alpha. Environment: running on the early access drop, with first tests passing on the main features and coverage collection started.
- RTL Completion: maturity 0.8, Beta. Environment complete for every feature at the RTL freeze. Results: regressions and coverage closure under way on the frozen RTL, with bugs going back to design.
- IP Verification: maturity 1.0, Released. Results: coverage goals met in every supported configuration; open bugs fixed or waived, and kept current while views and quality checks run.; Coverage closure
- IP DFT & Implementation Views: maturity 1.0, Released. Results: coverage goals met in every supported configuration; open bugs fixed or waived, and kept current while views and quality checks run.
- IP Quality Checks: maturity 1.0, Released. Results: coverage goals met in every supported configuration; open bugs fixed or waived, and kept current while views and quality checks run.
- IP Release & Hand-off: maturity Locked. Regression results locked with the release.
- IP FPGA prototyping
- RTL to Early Access: maturity 0.0, Specified. Prototype board chosen and the block partitioned for it.
- RTL Completion: maturity 0.3, Pre-alpha. Block running on its own on the board.; Standalone prototype available
- IP Verification: maturity 0.5, Alpha. Testing at speed with real interfaces and software.
- IP DFT & Implementation Views: maturity 0.8, Beta. Prototype tests complete on the verified RTL.
- IP Quality Checks: maturity 1.0, Released. Prototype results final; demonstrations ready for licensees.
- IP Release & Hand-off: maturity 1.0, Released. Prototype results final; demonstrations ready for licensees.
- IP emulation
- Micro-architecture: maturity 0.0, Specified. Need for emulation judged from the block's size, configurations and software load, with the harness approach and emulator capacity agreed with verification; nothing compiled yet.
- RTL to Early Access: maturity 0.3, Pre-alpha. Emulator set up and the early drop compiled.
- RTL Completion: maturity 0.5, Alpha. Long runs and the reference driver running on the frozen RTL.
- IP Verification: maturity 0.8, Beta. Emulation runs complete for sign-off, with results handed to verification.
- IP DFT & Implementation Views: maturity 1.0, Released. Emulation complete: results archived with the verified RTL, and the platform kept to reproduce issues found while views and quality checks run.
- IP design for test
- IP Specification & Architecture: maturity 0.0, Specified. Test requirements and access needs collected.
- Micro-architecture: maturity 0.0, Specified. Test requirements and access needs collected.
- RTL to Early Access: maturity 0.3, Pre-alpha. Test plan drafted against the micro-architecture and the early RTL.
- RTL Completion: maturity 0.5, Alpha. Test plan final; scan and self-test insertion started on the frozen RTL.
- IP Verification: maturity 0.8, Beta. Test structures inserted and checked on the verified RTL.
- IP DFT & Implementation Views: maturity 1.0, Released. Test patterns generated and coverage reported with the views.
- IP implementation views
- Micro-architecture: maturity 0.0, Specified. Constraints and target processes planned.
- RTL to Early Access: maturity 0.3, Pre-alpha. First timing constraints written for the early drop.
- RTL Completion: maturity 0.5, Alpha. Trial synthesis run on the frozen RTL, with constraints updated.
- IP Verification: maturity 0.8, Beta. Reference synthesis clean on the verified RTL; models being produced.
- IP DFT & Implementation Views: maturity 1.0, Released. Constraints, reference synthesis results and timing models final.; Views final
- IP Quality Checks: maturity 1.0, Released. Constraints, reference synthesis results and timing models final.
- Third-party IP intake
- IP Specification & Architecture: maturity 0.0, Specified. Suppliers evaluated and the licence agreed.
- Micro-architecture: maturity 0.3, Pre-alpha. Supplier deliveries planned against the micro-architecture needs.
- RTL to Early Access: maturity 0.5, Alpha. Early supplier delivery checked against what it should contain.
- RTL Completion: maturity 0.5, Alpha. Early supplier delivery checked against what it should contain.
- IP Verification: maturity 0.8, Beta. Feature-complete supplier delivery checked and its gaps raised.
- IP DFT & Implementation Views: maturity 0.8, Beta. Feature-complete supplier delivery checked and its gaps raised.
- IP Quality Checks: maturity 1.0, Released. Final supplier delivery accepted against the licence terms.
- IP Release & Hand-off: maturity 1.0, Released. Final supplier delivery accepted against the licence terms.
- IP quality and release
- IP Specification & Architecture: maturity 0.0, Specified. Quality checklist planned for this version.
- Micro-architecture: maturity 0.0, Specified. Quality checklist planned for this version.
- RTL to Early Access: maturity 0.3, Pre-alpha. Evidence list drafted from the early drop.
- RTL Completion: maturity 0.5, Alpha. Evidence collected from the frozen RTL: lint, clock domain crossing and test plans.
- IP Verification: maturity 0.8, Beta. Verification and view evidence collected; the checklist is being run.
- IP DFT & Implementation Views: maturity 0.8, Beta. Verification and view evidence collected; the checklist is being run.
- IP Quality Checks: maturity 1.0, Released. Quality checklist passed on the complete deliverable set.
- IP Release & Hand-off: maturity Locked. Release package locked; fixes come in a new version.; Release locked
- IP product management
- IP Specification & Architecture: maturity 0.0, Specified. Business case approved and the integrators named.
- Micro-architecture: maturity 0.3, Pre-alpha. Integrator agreements for early access drafted.
- RTL to Early Access: maturity 0.5, Alpha. Early access released to integrators, with its limits stated.
- RTL Completion: maturity 0.8, Beta. Adopting programmes confirmed and licence terms complete.
- IP Verification: maturity 1.0, Released. Release plan, support plan and announcement ready.
- IP DFT & Implementation Views: maturity 1.0, Released. Release plan, support plan and announcement ready.
- IP Quality Checks: maturity 1.0, Released. Release plan, support plan and announcement ready.
- IP Release & Hand-off: maturity Locked. Version released with its integration guide and support route.
For members, each lifecycle's own page opens with its chart at a glance, then why the chart looks as it does and the chart read stage by stage; select a lifecycle above or in the map. The product lifecycle's fit chart shows where every engineering lifecycle fits inside it, stage by stage.
Starting a chip company and not sure which of these lifecycles to follow? The startup lifecycle ready reckoner asks about your product, markets, team and supply, recommends the lifecycles, gates and checks to use now, and lets you tailor the gates.
To run a programme on one of these lifecycles, the product and project planner turns it into a plan with phases, gates and tasks, schedules it with a critical path, and tracks it with baselines, a RAID log, change control, gate reviews and reports for each role.
The lettered markers on each lifecycle's chart are the Hub's editorial notes on where AI is changing chip work. How AI is changing the lifecycle: the key and every note
Reading the charts: maturity, rules and TR gates
Each block shows how mature a discipline's work is by the end of a stage: 0.0 started, 0.3 early draft (outline and key choices in place, most content still to come), 0.5 in progress, 0.8 feature complete, 1.0 complete, then frozen. Each lifecycle names its own steps in its chart key.
Every chart follows the same rules. A discipline climbs at most one step a stage and never down. Each gate is owned by one discipline, which stands on the gate's step when it is held. A discipline is never ahead of the work it uses. A faded block, labelled Held or Maintained, means the step is held, or finished work is maintained under change control, and a hollow diamond is a milestone for one item while the rest of the work carries on. For members, each lifecycle's page sets these out under "Why the chart looks like this", for example for the SoC lifecycle.
TR Technical readiness review (TR): a gate that checks the technology is ready before the next commitment. TR1 checks technology and concept feasibility before development is committed (for a design kit, before the first release customers design on), TR2 design or technology readiness before a freeze or tape-out, and TR3 that the technology is ready for production before release. Where an existing gate already makes the check, it carries the TR tag instead of a new gate. TR in the glossary
How the lifecycles hand off to the product lifecycle
The product lifecycle sits in the middle. 476 gates across 35 engineering lifecycles feed a product gate or are the same decision as one (204 of them the same decision), and 124 product gate hand-downs start their stages. Inside chip and IP design, 5 IP releases also feed SoC gates directly. Where each lifecycle fits, stage by stage
- Chip and IP designIn212Out45
- Systems and platformsIn30Out8
- Software, security and AIIn34Out11
- Process, packaging and manufacturingIn78Out27
- Regulated marketsIn80Out20
- Quality and process assessmentIn24Out10
- Building a chip companyIn18Out3
In: gates that feed or match a product gateOut: product gate hand-downs that start the family's stages
Show this chart as a list
Where the IP lifecycles meet the SoC
Each Soft IP and Hard IP release feeds gates in the SoC lifecycle. The SoC team integrates what the two IP lifecycles hand over.
SoC teams start integration and floorplanning on an early drop, knowing its limits.
Hands over: Early access release, IP transaction-level model. Worked on in the SoC stages IP Integration.
The released package is what the SoC integrates, freezes its RTL with, tests and signs off.
Hands over: IP release package, Integration guide, Timing models, IP test patterns. Worked on in the SoC stages SoC RTL Design, Full-Chip DFT, Physical Design & Sign-off.
SoC teams place the macro and plan the floorplan, pins and power around its early abstract and preliminary timing, knowing they will change.
Hands over: Early views, Integration guide. Worked on in the SoC stages IP Integration, Physical Design & Sign-off.
The signed-off layout and characterised views are what the SoC merges and signs off with, accepting that the macro is not yet proven on silicon.
Hands over: GDS layout, Characterised views, Integration guide. Worked on in the SoC stages Physical Design & Sign-off.
Silicon results, errata and views correlated with silicon tell the SoC's tape-out readiness review how much risk the macro still carries.
Hands over: Silicon report, Silicon-correlated views, Silicon errata. Worked on in the SoC stages Tape-out.
Work products
Each document, model and item the disciplines bring to the gates has its own page: who makes it, who uses it and how mature it should be at each gate.
All lifecycle work products →