Tools
All tools in one place: the Hub's own calculators and utilities, and an index of the tools engineers use across the industry. Usable without sign-in. Sign in to save your inputs and subscribe to MPW shuttle alerts.
Hub utilities
Gross-die yield off wafer size, die size and edge exclusion.
Poisson-model gross-die yield from defect density.
Parametric per-unit cost: silicon, package, test, NRE.
Full AI-accelerator cost bridge: logic die, HBM, packaging and test.
Compare CoWoS-S, CoWoS-L, EMIB, SoIC and flip-chip cost and HBM-stack support.
Side-by-side manufacturing cost comparison across AI accelerators.
Compare accelerators on cost, throughput and TCO.
Foundry, CoWoS and HBM allocation status across fabs and process nodes.
Guided workflow for fabless teams evaluating a tapeout: definition through go/no-go.
mm, mil, µm, inch, cm: the ones you actually convert between.
Upload a PDF, ask questions with page citations, extract and compare parameters. Paid plans.
Classify a change into one of the Hub's ten product types and see its obligations, deliverables and gates.
Upload a schematic or BOM PDF for a general sanity check: not a substitute for real DRC/ERC tooling. Paid plans.
Net income plus interest, taxes, depreciation and amortization, with margin.
Return on investment, plus an annualized rate over a holding period.
Compound annual growth rate between a beginning and ending value.
COGS, ASP, margin, breakeven, NRE payback, NPV/IRR and TAM/SAM/SOM for a semiconductor product: savable, with an AI viability narrative.
Plan, schedule and track a programme on any Hub lifecycle: Gantt chart with critical path, baselines, RAID log, change control, gate reviews, role reports and MS Project XML export. Paid plans.
Where along the chip lifecycle the utilities help
How many Hub utilities are tagged to each lifecycle stage, in the order the stages run. Select a stage to see its utilities.
- SoC Specification & Architecture (SoC lifecycle)10
- Physical Design & Sign-off (SoC lifecycle)1
- Tape-out (SoC lifecycle)2
- Foundry & Mask (SoC lifecycle)2
- Packaging & Test (SoC lifecycle)2
- Bring-up & Silicon Validation (SoC lifecycle)1
- Production Ramp & Yield (SoC lifecycle)3
- IP Specification & Architecture (Soft IP lifecycle)1
- Interposer & Substrate Design (Chiplet lifecycle)1
Show this chart as a list
Engineering tools
Calculators, worksheets and planners for the work along the chip lifecycles, each on its own page with its method, assumptions and sources. Calculators are free to use; worksheets, checklists, trackers and planners are for members.
Cost and business
Mask, wafer, test and bill of materials costs, sourcing choices and end-of-life buys.
- Mask set cost estimatorFreePrice a photomask set layer by layer for any node from 180 nm to 2 nm, then add spares, re-spins, metal-only fixes and replacement sets over your volume.Helps in 22 lifecycle stages
- Wafer cost modelFreeBuild up the cost of a processed wafer from fab capital, depreciation, mask steps, materials, labour and utilisation, then compare it with published foundry prices by node.Helps in 4 lifecycle stages
- Test time and cost estimatorFreeEstimate test time per unit and the test cost each good part carries, across wafer sort, final test and burn-in, with tester rates, multisite and retest.Helps in 22 lifecycle stages
- Die area estimatorFreeEstimate die area from logic gates, memory bits, analog and IP blocks, input and output count and placement density, and see whether the die is pad or core limited.Helps in 8 lifecycle stages
- MPW shuttle cost plannerFreePlan a multi-project wafer run: block area, price per square millimetre, die delivered and extra runs, and the point where a dedicated mask set pays off.Helps in 8 lifecycle stages
- Last-time buy calculatorFreeSize a last-time buy from forecast demand, failure returns, safety stock and support years, net of stock in hand, with holding cost and scrap risk.Helps in 26 lifecycle stages
- IP make or buy comparisonFreeCompare building a block in-house with licensing it, on cost, schedule, risk and royalties over the product's volume and life, with the break-even volume.Helps in 8 lifecycle stages
- FPGA, structured ASIC or ASIC crossover calculatorFreeFind the volumes where an FPGA, a structured ASIC and a full ASIC each cost least, from engineering cost, unit price and time to market.Helps in 6 lifecycle stages
- Memory bit cost estimatorFreeEstimate DRAM or NAND cost per gigabit from wafer cost, die size, density, layers, bits per cell and yield, and how it moves with each lever.Helps in 3 lifecycle stages
- Bill of materials cost roll-upFreeRoll up a bill of materials with quantities, price breaks, scrap and minimum order quantities, add assembly, test and overhead, and see the cost at each volume.Helps in 2 lifecycle stages
- Equipment cost of ownership calculatorFreeWork out the cost of each good wafer pass through a tool from its price, depreciation, floor space, consumables, labour, throughput, uptime and yield.Helps in 4 lifecycle stages
- Platform reuse savings calculatorFreeWeigh a shared platform against standalone designs: up-front cost, reuse share, savings per derivative, time saved and the number of variants to break even.Helps in 2 lifecycle stages
Reliability
Failure rates, stress tests, qualification plans and radiation effects.
- Failure rate (FIT) calculatorFreeTurn life test results into a failure rate in FIT and a mean time to failure at use conditions, with chi-squared confidence and acceleration from several test legs.Helps in 13 lifecycle stages
- Stress test acceleration factor calculatorFreeWork out how much faster a stress test ages a part than use does: Arrhenius, Eyring, Peck, Coffin-Manson, Norris-Landzberg, voltage and Black's equation.Helps in 3 lifecycle stages
- Qualification test plannerMembersBuild a reliability qualification plan for your product grade and package: which stress tests apply, lots, sample sizes, conditions, durations, devices and schedule.Helps in 24 lifecycle stages
- Defect level (DPPM) estimatorFreeEstimate the defective parts per million that escape test from fault coverage and yield with the Williams-Brown and Agrawal models, and the coverage a DPPM target needs.Helps in 6 lifecycle stages
- Error rate confidence calculatorFreePut confidence bounds on an error rate from errors seen in trials, find the trials needed to show a target rate, and size bit error rate tests.Helps in 5 lifecycle stages
- Lot sampling plan calculatorFreeDesign an attribute sampling plan from AQL, LTPD and the producer and consumer risks, see its operating characteristic curve, and compare zero-acceptance plans.Helps in 3 lifecycle stages
- Stack and multi-die yield calculatorFreeEstimate the yield of a die stack or multi-die package from die yield, known-good-die test escapes, bond yield per interface, repair and assembly yield.Helps in 6 lifecycle stages
- Radiation dose margin calculatorFreeCompare a part's total ionising dose rating with the mission dose behind its shielding, and check the radiation design margin a programme requires.Helps in 3 lifecycle stages
- Single-event upset rate estimatorFreeEstimate single-event upset rates from Weibull cross-section parameters or the figure of merit method, for heavy ions and protons, with scrubbing and error correction.Helps in 3 lifecycle stages
- Component derating checkerFreeCheck each part's applied stress against its rating and the derating rule for its type, and list the parts that pass, fail or sit close to the limit.Helps in 4 lifecycle stages
- Mission profile builderMembersBuild a use profile phase by phase and turn it into the equivalent hours and cycles of the qualification stresses, to see whether the standard tests cover it.Helps in 2 lifecycle stages
- Warpage and thermal mismatch estimatorFreeEstimate warpage and solder joint strain from thermal expansion mismatch between die, substrate, mould and board, with a fatigue life estimate.Helps in 5 lifecycle stages
Quality statistics
Process capability, measurement systems, control charts and test limits.
- Process capability (Cpk) calculatorFreeCompute Cp, Cpk, Pp, Ppk and Cpm from your data or summary figures, with confidence bounds, expected parts per million out of specification and a histogram.Helps in 13 lifecycle stages
- Gauge repeatability and reproducibility calculatorFreeRun a crossed gauge study by the ANOVA or the average and range method: repeatability, reproducibility, part variation, percent of tolerance and distinct categories.Helps in 3 lifecycle stages
- Statistical process control chartFreeDraw X-bar and R, X-bar and S, individuals and moving range, p, np, c and u charts from your data, with control limits and the run rules that flag a process out of control.Helps in 10 lifecycle stages
- Test limit and guard band calculatorFreeSet test limits inside the specification for measurement uncertainty, and see the false accept and false reject rates and the yield each guard band costs.Helps in 3 lifecycle stages
- Outlier screening (PAT) limit calculatorFreeSet static and dynamic part average testing limits from robust statistics, flag the outliers in your data and see the yield the screen removes.Helps in 1 lifecycle stage
- Yield learning curve projectorFreeProject yield over a ramp from defect density learning per doubling of volume or over time, and see when the target yield and good die volumes are reached.Helps in 5 lifecycle stages
- Bin and grade mix plannerFreeSplit a speed or power distribution into bins, fill demand with down-binning, and see the revenue and average selling price per wafer for each bin plan.Helps in 2 lifecycle stages
- Sensor calibration fit toolFreeFit calibration data with a straight line or a polynomial, with optional temperature terms, and see the residuals, non-linearity, hysteresis and maximum error.Helps in 1 lifecycle stage
- Sensor error budget builderFreeList a sensor chain's error sources in their own units, convert them to one basis and combine them worst case and root sum square against the accuracy target.Helps in 2 lifecycle stages
- Process assessment rating calculatorFreeRate process attributes on the N, P, L, F scale from indicator scores and derive each process's capability level against a target profile, Automotive SPICE style.Helps in 3 lifecycle stages
Quality worksheets
FMEA, control plans, 8D, traceability and the other records audits ask for.
- FMEA worksheetMembersWork through design or process failure modes, effects, causes and controls, rank them by risk number or an editable action priority rule, and track the actions to closure.Helps in 14 lifecycle stages
- Control plan builderMembersBuild a control plan for prototype, pre-launch or production: characteristics, special characteristics, measurement, sample size and frequency, control method and reaction plan.Helps in 8 lifecycle stages
- 8D problem solving report builderMembersRun an 8D report from team and problem description through containment, root cause, corrective and preventive action to closure, with dates, age and completeness.Helps in 3 lifecycle stages
- PPAP element checklistMembersTrack the eighteen production part approval elements for a submission level: which are submitted or retained, the owner, due date, evidence and completion.Helps in 3 lifecycle stages
- Requirements traceability matrixMembersLink requirements to design elements, verification methods, tests and results, and see coverage, orphans, failing links and gaps by requirement type.Helps in 32 lifecycle stages
- Product change impact checkerMembersCheck a product or process change against a question list by change type, and see the impact areas, requalification tests and customer notice it needs.Helps in 12 lifecycle stages
- Errata log builderMembersRecord each known difference from the specification with its workaround, affected steppings and customer wording, and export the public errata sheet.Helps in 12 lifecycle stages
- Audit finding and action trackerMembersTrack audit findings by type and clause with root cause, correction, corrective action, owner, due dates and effectiveness checks, with ageing and overdue counts.Helps in 7 lifecycle stages
- Internal audit programme plannerMembersPlan internal audits by risk: frequency per area, last result, auditor, next due date, a twelve-month calendar and the clauses each audit covers.Helps in 1 lifecycle stage
- Interface agreement responsibility matrixMembersAgree who is responsible for each safety activity and work product between customer and supplier, with approvals, phases and unassigned items flagged.Helps in 2 lifecycle stages
- IP deliverables checklist builderMembersBuild the list of views, models and documents an IP release must contain for its type, and check a release against it for readiness.Helps in 8 lifecycle stages
- PDK release maturity checklistMembersTrack a process design kit's decks, models, libraries and documents against each release stage, and see readiness per stage and what blocks the next one.Helps in 5 lifecycle stages
Safety and security
Functional safety metrics, integrity levels, threat and vulnerability ratings.
- Hardware safety metrics calculatorFreeCompute the single point fault metric, latent fault metric and probabilistic hardware failure metric from an FMEDA-style list, against the targets for each ASIL.Helps in 3 lifecycle stages
- Safety integrity level determinationFreeDetermine an ASIL from severity, exposure and controllability, a SIL from an editable risk graph, and the assurance levels used in aerospace and medical software.Helps in 2 lifecycle stages
- Fault tree calculatorFreeBuild a fault tree from AND, OR and voting gates over basic events, and get the top event probability, minimal cut sets and importance of each event.Helps in 2 lifecycle stages
- Fault injection campaign sizerFreeSize a fault injection campaign: injections needed for a diagnostic coverage estimate at a confidence, simulation time, licences and calendar time.Helps in 4 lifecycle stages
- Safety function failure probability calculatorFreeCompute the average probability of failure on demand or the failure frequency per hour for 1oo1, 1oo2, 2oo2, 1oo2D and 2oo3 architectures, with the SIL reached.Helps in 2 lifecycle stages
- Threat risk assessment calculatorFreeRate threat scenarios by impact and attack feasibility from attack potential, derive the risk value from an editable matrix, and record the treatment.Helps in 6 lifecycle stages
- Vulnerability severity calculatorFreeScore a vulnerability with CVSS version 3.1 or 4.0 base, threat and environmental metrics, and read or write the vector string.Helps in 10 lifecycle stages
- Side-channel leakage assessmentFreeRun a fixed versus random Welch t-test on side-channel traces or summary statistics, flag leaky points against the threshold, and size the traces needed.Helps in 2 lifecycle stages
- Software update impact assessmentMembersAssess whether a software update touches type-approved functions, safety or cybersecurity, and list the records and approvals the update management system needs.Helps in 4 lifecycle stages
- SBOM licence checkerFreePaste a software bill of materials and see each component's licence class, the obligations for your distribution model and any conflicts or unknown licences.Helps in 3 lifecycle stages
- Development assurance objectives checklistMembersTrack the development assurance objectives for each assurance level, with independence, evidence and completion by process area, for airborne hardware and software.Helps in 2 lifecycle stages
- Medical device classification helperFreeWork through the EU classification rules for a medical device and its software step by step, and see the class, the rule that applied and the conformity route.Helps in 1 lifecycle stage
Digital and physical design
Power, thermal, area, interconnect and the design records engineers keep.
- Power and thermal estimatorFreeEstimate a chip's dynamic and leakage power from activity, capacitance, voltage and frequency, and its junction temperature from the package and cooling.Helps in 13 lifecycle stages
- Power tree and budget calculatorFreeBuild a board or system power tree of rails, regulators and loads, and see each rail's current, converter losses, efficiency and total input power.Helps in 2 lifecycle stages
- Register map builderMembersDefine registers and their fields once, check addresses, widths and overlaps, and produce the documentation table and the C header that software uses.Helps in 7 lifecycle stages
- Coverage closure trackerMembersTrack code, functional and assertion coverage goals for each block over time, and project when verification will close from the trend.Helps in 6 lifecycle stages
- FPGA resource and device sizing estimatorFreeEstimate logic, memory, DSP, transceiver and IO needs from your blocks, add margin, and see which device sizes fit and how full each would be.Helps in 5 lifecycle stages
- Logic density estimatorFreeEstimate standard cell logic density from contacted gate pitch, metal pitch, cell height and design utilisation, and compare nodes on a common basis.Helps in 2 lifecycle stages
- Interconnect RC calculatorFreeWork out wire resistance, capacitance and delay from line width, thickness, spacing, dielectric and resistivity with size effects, for any metal layer.Helps in 2 lifecycle stages
- Electromigration wire width calculatorFreeWork out the wire width and number of vias a net needs for the current it carries, from the foundry's current density limits and the use temperature.Helps in 2 lifecycle stages
- Layer density and fill calculatorFreeCheck layer density per window against minimum and maximum rules, and estimate the fill needed and its effect on capacitance.Helps in 1 lifecycle stage
- Model to silicon correlation viewerFreeCompare measured silicon results with simulated or characterised values across corners, and flag the parameters that differ beyond their limits.Helps in 1 lifecycle stage
- Hard IP port effort estimatorFreeEstimate what porting a hard macro to another process or metal stack involves, from its mix of custom, compiled and digital content and the change.Helps in 1 lifecycle stage
Analog, RF, photonics and packaging
Converters, RF chains, matching, links and package electrical limits.
- Data converter SNR and ENOB calculatorFreeWork out ADC and DAC signal-to-noise ratio, SINAD, effective number of bits, noise floor and dynamic range from resolution, jitter, noise and distortion.Helps in 2 lifecycle stages
- RF cascade and link budget calculatorFreeCascade gain, noise figure and intercept points through an RF chain stage by stage, and build a link budget from transmit power to receiver sensitivity.Helps in 1 lifecycle stage
- Impedance matching network calculatorFreeDesign L, Pi and T matching networks between two impedances at a frequency, with component values, bandwidth and the nearest standard parts.Helps in 2 lifecycle stages
- S-parameter viewerFreePaste Touchstone data and see return loss, insertion loss, VSWR, group delay and stability across frequency, with conversions between formats.Helps in 1 lifecycle stage
- Transmission line impedance calculatorFreeWork out the impedance, delay and loss of microstrip, stripline and coplanar lines from trace geometry and the dielectric, with differential pairs.Helps in 7 lifecycle stages
- Die-to-die link bandwidth estimatorFreeEstimate die-to-die bandwidth, shoreline density, area and energy per bit from lanes, data rate, bump pitch and the interface standard.Helps in 1 lifecycle stage
- Optical link budget calculatorFreeAdd up transmitter power, fibre and connector losses, penalties and receiver sensitivity to see the link margin and the reach it allows.Helps in 2 lifecycle stages
- Fibre coupling loss calculatorFreeEstimate coupling loss between fibres, waveguides and lasers from mode field mismatch, offset, tilt, gap and reflection.Helps in 2 lifecycle stages
- Power device loss calculatorFreeWork out conduction and switching losses of silicon, SiC and GaN devices in a converter, and the junction temperature from the thermal path.Helps in 4 lifecycle stages
- Creepage and clearance calculatorFreeLook up the creepage and clearance a working voltage needs for its pollution degree, material group, overvoltage category and altitude.Helps in 3 lifecycle stages
Manufacturing, fab and supply
Capacity, equipment, cleanrooms, spares and supply decisions.
- Capacity ramp plannerFreePlan a fab or line ramp month by month: tool install and qualification, wafer starts, cycle time, yield and the output that reaches customers.Helps in 10 lifecycle stages
- Wafer bank plannerFreeSize a bank of partly processed base wafers for structured ASICs or platforms: demand, lead times, safety stock, holding cost and the time to finish.Helps in 2 lifecycle stages
- Spare parts stocking calculatorFreeWork out how many spares to hold for a fleet of tools from failure rates, repair times and the availability you need, with a Poisson stock model.Helps in 1 lifecycle stage
- Equipment availability calculatorFreeTurn equipment time states into availability, uptime, utilisation and overall equipment effectiveness, after the SEMI E10 states and E79 measures.Helps in 4 lifecycle stages
- Fab utility demand estimatorFreeEstimate a fab's electricity, ultrapure water, cooling, nitrogen and other utility demand from wafer starts, node and cleanroom size.Helps in 2 lifecycle stages
- Cleanroom class calculatorFreeWork out an ISO 14644-1 cleanroom class from particle counts, the particle limits for a class and size, and the sample locations and volumes a test needs.Helps in 1 lifecycle stage
- Permit and incentive conditions trackerMembersTrack the permits a fab needs and the conditions attached to grants and incentives, with milestones, evidence, due dates and money at risk.Helps in 1 lifecycle stage
- Weighted decision matrixFreeCompare options against weighted criteria, with scoring scales, must-have gates, sensitivity to the weights and a ranked result.Helps in 10 lifecycle stages
- Product variant matrixMembersLay out a product family's variants against features, packages, grades and options, and check coverage, duplicates and the parts each variant needs.Helps in 3 lifecycle stages
AI, systems and startup
AI compute sizing, certification, schedules, pipelines and company finance.
- Roofline performance modelFreePlot attainable performance against arithmetic intensity for a chip's compute and memory limits, and place your kernels and models on it.Helps in 5 lifecycle stages
- AI model memory and bandwidth sizerFreeSize the memory and bandwidth an AI model needs for training or inference: weights, activations, optimiser state, KV cache, precision and batch.Helps in 2 lifecycle stages
- Cluster network sizerFreeSize an AI cluster network: accelerators, links, switch radix, fat-tree tiers, oversubscription, optics count, power and collective communication time.Helps in 1 lifecycle stage
- AI tool data and licence checklistMembersCheck an AI tool before you use it on design data: where data goes, what is retained, licence terms for outputs, export control and approvals.Helps in 2 lifecycle stages
- Certification test plannerMembersPlan the certification tests a system or product needs by market: safety, EMC, environmental and energy, with labs, durations, costs and schedule.Helps in 2 lifecycle stages
- Radio certification plannerMembersPlan radio approvals by country and band: the rules, tests, modular approval options, lead times and costs for each market.Helps in 2 lifecycle stages
- Schedule risk estimatorFreeEstimate how likely a programme date is from three-point stage estimates and risks on the critical path, with a Monte Carlo simulation.Helps in 8 lifecycle stages
- Design win pipeline forecastMembersTrack design-in opportunities by stage, probability, volume and price, and forecast the revenue they bring year by year.Helps in 3 lifecycle stages
- Startup runway and burn calculatorFreeWork out a startup's burn and runway month by month from cash, headcount, spend, tape-out costs, revenue and funding, with what-if scenarios.Helps in 3 lifecycle stages
- Cap table and dilution calculatorFreeModel a cap table through funding rounds: pre-money, option pool, SAFEs and notes, dilution per holder and the exit waterfall.Helps in 3 lifecycle stages
Industry tools index
135 of 4,606 tools, ranked by how many roles use each one. Category and company are a best-effort match on the tool's name, not a hand-curated taxonomy.
Sequential logic synthesis and formal verification tool from UC Berkeley, used inside Yosys and OpenROAD flows.
Python-based hardware description language and toolchain for building digital designs.
Agentless automation tool for configuring systems, deploying software and orchestrating IT tasks from readable playbooks.
Workflow platform for authoring, scheduling and monitoring data pipelines as Python code.
Machine-learning compiler that optimizes trained models to run efficiently on CPUs, GPUs and specialized accelerators.
Fast, reproducible build and test system for large multi-language codebases.
Dependency manager for hardware projects, from the PULP platform.
Python-based circuit automatic characterization engine: runs simulations across conditions to check an analog block against its specification.
Characterization tool that measures standard cells and produces timing and power libraries.
GUI and command-line wrapper for mismatch simulation, parameter sweeps and yield analysis of analog circuits.
Version manager and builder for open-source PDKs, for installing and switching between PDK versions.
Cross-platform build-system generator that produces Makefiles and project files for C and C++ software.
Python library for writing testbenches that drive VHDL and Verilog simulators.
Verilog code coverage tool that shows how much of a design a testbench exercises.
Circuit validity checker that runs electrical rule checks on transistor-level netlists.
Container platform for packaging an application with its dependencies so it runs the same everywhere.
Documentation generator that builds reference docs from annotated source code, mainly C and C++.
Python library giving one interface for running simulators, synthesis and FPGA tools from a project description.
Distributed search and analytics engine for full-text search, logs and other large datasets.
Capacitance extraction tool, part of the RF toolkit.
Inductance and impedance extraction tool, part of the RF toolkit.
Design-for-testing solution that inserts scan chains and generates test patterns for digital chips.
All-in-one container of open-source tools for SKY130-based analog and digital design.
Package manager and build system for reusable hardware cores and SoC projects.
Waveform viewer for plotting Xschem and ngspice simulation results.
GNU debugger for stepping through programs, inspecting memory and diagnosing crashes, including on embedded targets.
Setup tools that turn GDSII layouts into models for electromagnetic simulation with Palace.
3D viewer that renders GDSII layouts layer by layer.
Rust design-rule-check engine for GDSII layouts, with rules written in YAML decks.
Python library for generating chip layouts (GDS) from code, widely used for photonic and analog designs.
Rust tool that inserts dummy metal fill into layouts to meet density rules.
Python module for creating and manipulating GDSII layout files.
Modular computer-architecture simulator used to model CPUs, caches and memory systems before hardware exists.
Open-source process design kit for the GlobalFoundries 180 nm CMOS process.
Open-source VHDL simulator and compiler.
Yosys plugin that adds VHDL synthesis by using GHDL as the front end.
Distributed version control system for tracking source changes and collaborating on code.
Web platform for hosting Git repositories with code review, issue tracking and built-in CI/CD.
Continuous integration and delivery system built into GitLab, configured through a pipeline file in the repository.
Three-dimensional finite element mesh generator used to prepare geometry for electromagnetic and physical simulation.
Dashboarding tool for visualizing metrics, logs and other time-series data from many sources.
Waveform viewer for the results of digital simulation.
Python library for describing analog and mixed-signal hardware as code.
Open-source Verilog simulator and compiler.
Bitstream documentation and tools for Lattice iCE40 FPGAs.
Open-source PDK for IHP Microelectronics' 130 nm CMOS process (M1-M4-TM1 metal stack).
Open-source PDK for IHP's 130 nm SiGe:C BiCMOS process, suited to RF and high-speed analog.
All-in-one Docker and Podman container bundling open-source tools and PDKs for analog and digital chip design.
Switch-level simulator for digital MOS circuits.
Automation server for building, testing and deploying software through configurable CI/CD pipelines.
Interactive documents that mix live code, results, charts and notes, widely used for data analysis and prototyping.
Graphical editor for IP-XACT files, used to package and integrate IP blocks.
Logic equivalence checking tool for the OpenROAD flow, confirming two versions of a design behave the same.
Open-source suite for schematic capture and printed circuit board layout.
Layout viewer and editor for GDS and OASIS files, with scripting and design-rule checking.
Parasitic extraction (PEX) package for KLayout.
Collection of KLayout plugins from IIC-JKU that speed up everyday layout work.
Orchestration system for deploying, scaling and managing containerized applications across clusters.
Characterization kit for CMOS cells that extracts timing and power into library files.