FPGA, structured ASIC or ASIC crossover calculator
Find the volumes where an FPGA, a structured ASIC and a full ASIC each cost least, from engineering cost, unit price and time to market.
Cost and businessFree to useHow it worksSourcesWhere it helps
Fills the inputs below with typical figures. Replace any of them with your own.
- Cheapest at 200,000 units
- Structured ASIC
- $10,800,000 in total, $2,400,000 less than ASIC, with the time-to-market penalty
- FPGA: total cost
- $21,500,000
- $107.50 a unit including NRE
- Structured ASIC: total cost
- $10,800,000
- $54.00 a unit including NRE
- ASIC: total cost
- $13,200,000
- $66.00 a unit including NRE
- Crossover: FPGA and structured ASIC
- 27,419 units
- Without the penalty: 24,194 units
- Crossover: structured ASIC and ASIC
- 320,000 units
- Without the penalty: 300,000 units
- Crossover: FPGA and ASIC
- 98,780 units
- Without the penalty: 91,463 units
- Time to market
- 6, 10 and 18 months
- FPGA, structured ASIC and ASIC
- FPGA$21,500,000
- Structured ASIC$10,800,000cheapest
- ASIC$13,200,000
Show the data as a table
| Item | Total cost (USD) |
|---|---|
| FPGA | $21,500,000 |
| Structured ASIC | $10,800,000 |
| ASIC | $13,200,000 |
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- FPGA (solid line, circles)
- Structured ASIC (dashed line, squares)
- ASIC (dotted line, triangles)
Show the data as a table
| Lifetime volume (units) | FPGA | Structured ASIC | ASIC |
|---|---|---|---|
| 1,000 | $605,000 | $2.24 m | $8.62 m |
| 2,000 | $710,000 | $2.29 m | $8.65 m |
| 5,000 | $1.02 m | $2.42 m | $8.71 m |
| 10,000 | $1.55 m | $2.63 m | $8.83 m |
| 20,000 | $2.6 m | $3.06 m | $9.06 m |
| 50,000 | $5.75 m | $4.35 m | $9.75 m |
| 100,000 | $11 m | $6.5 m | $10.9 m |
| 200,000 | $21.5 m | $10.8 m | $13.2 m |
| 500,000 | $53 m | $23.7 m | $20.1 m |
| 1,000,000 | $106 m | $45.2 m | $31.6 m |
| 2,000,000 | $211 m | $88.2 m | $54.6 m |
| 5,000,000 | $526 m | $217 m | $124 m |
| 10,000,000 | $1.05 bn | $432 m | $239 m |
| Item | FPGA | Structured ASIC | ASIC |
|---|---|---|---|
| Design engineering | $400,000 | $1,000,000 | $4,000,000 |
| Masks and fab set-up | $0 | $600,000 | $2,500,000 |
| IP and tool licences | $60,000 | $250,000 | $1,000,000 |
| Test development | $40,000 | $150,000 | $500,000 |
| One-off cost (NRE) | $500,000 | $2,000,000 | $8,000,000 |
| Devices | $20,000,000 | $8,000,000 | $4,000,000 |
| Board cost | $1,000,000 | $600,000 | $600,000 |
| Energy over the unit life | $0 | $0 | $0 |
| Time-to-market penalty | $0 | $200,000 | $600,000 |
| Total cost | $21,500,000 | $10,800,000 | $13,200,000 |
| Cost per unit including NRE | $107.50 | $54.00 | $66.00 |
| Months to market | 6.0 | 10.0 | 18.0 |
| Power per unit (W) | 8 | 4 | 2 |
| Options | Without the penalty | With the penalty | Cheaper below the crossover |
|---|---|---|---|
| FPGA and Structured ASIC | 24,194 units | 27,419 units | FPGA |
| Structured ASIC and ASIC | 300,000 units | 320,000 units | Structured ASIC |
| FPGA and ASIC | 91,463 units | 98,780 units | FPGA |
How it works
At what volume does a custom chip pay for itself? This tool puts an FPGA, a structured ASIC and a full ASIC side by side, with the one-off cost, the unit cost and the time to market of each, and finds the volumes where one overtakes another. It can add the revenue lost to a later launch and the cost of power over the unit's life.
- Add up the one-off cost (NRE). Each option has four one-off items: design engineering, masks and fab set-up, IP and tool licences, and test development (which includes qualification). An FPGA has almost no masks, and its design effort is real but smaller; a structured ASIC changes only a few metal layers; a full ASIC pays for a complete mask set and the longest design.
NRE = design engineering + masks and fab set-up + IP and tool licences + test development - Price each unit. The unit cost is the device price plus any difference in board cost (power supplies, configuration memory, cooling). An ASIC can be entered as one figure or as die, package and test. A volume tier lets the price fall above a chosen volume: only the units above it get the lower price. Costs paid across the product life are discounted by the average discount factor of the years.
discount factor = average over years t = 1 to N of 1 / (1 + r)^t; unit cost = (device price + board cost) x discount factor + energy per unit; device price above the tier = price x tier share - Energy over the life (optional). If you choose to include energy, each unit carries the cost of the power it draws over its service life. This matters where the customer pays for power and the FPGA draws several times what a custom chip does. It is not discounted.
energy per unit = power (W) / 1000 x hours per year x service years x price per kWh - Count the time-to-market penalty. An option that reaches the market later than the fastest one loses sales. Enter the revenue lost for each month of delay, or a revenue per unit that is spread over the product life. The penalty is measured against the fastest option, so it is zero for that one.
penalty = (months to market − fastest months to market) x lost revenue per month; or (months − fastest months) x revenue per unit x volume / (12 x years) - Total cost at a volume. The total cost of an option is its NRE, its penalty and its unit cost for every unit. The cost per unit including NRE is the total divided by the volume. The cheapest option at your volume is the one with the lowest total.
total(V) = NRE + penalty + unit cost x V; cost per unit = total(V) / V - Solve the crossovers. Two totals meet where their NRE difference is paid back by the unit cost difference. With a volume tier the cost has a bend, so the tool solves each straight stretch exactly. The result is given with and without the time-to-market penalty, because a later launch moves every crossover to a higher volume for the slower option.
crossover volume = (NRE of the higher-NRE option + its penalty − NRE of the lower-NRE option − its penalty) / (unit cost of the lower-NRE option − unit cost of the higher-NRE option)
Assumptions
- All money is in US dollars. Unit prices are per device at the volume entered, and the same price applies to every unit up to the tier.
- An FPGA has a real design cost, because place and route and timing closure take engineering effort, even though it needs no masks.
- The FPGA design is assumed to be moved to the structured ASIC or the ASIC with no change in function, and the one-off cost already includes that conversion.
- The time-to-market penalty counts revenue lost to a later launch against the fastest option. It is not discounted.
- Volume is the lifetime volume; every unit is sold at the unit cost entered. Yield loss and scrap are not modelled: put them in the unit price.
- The preset figures are editorial estimates for typical cases. They are not quotes and not reported prices.
Limits and warnings
- Real prices depend on the exact device, the node, the quantity and the negotiation. Treat any result as a screening figure and replace the inputs with quotes.
- Technical fit is not priced: the performance, power and area gap between an FPGA and a custom chip, and the risk of a re-spin, decide whether the ASIC can be used at all.
- Respins, redesigns and field updates are not included unless you add them to the NRE. An FPGA can be updated in the field; an ASIC cannot.
- Supply and obsolescence risk, such as the end of life of an FPGA family, are not priced.
- Mask costs change greatly with the node. See the mask set cost estimator (/tools/mask-cost-estimator) for the mask part of the ASIC NRE.
- The chart covers 1,000 to 10 million units. A volume outside that range is still calculated exactly in the totals and crossovers.
Sources
The methods and default figures rest on these public sources. The wording here is our own; read the source for its full text.
- Measuring the Gap Between FPGAs and ASICs (opens in a new tab), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 26, number 2 (Ian Kuon and Jonathan Rose), February 2007. The area, speed and power gaps between 90 nm FPGAs and standard-cell ASICs, which is why the unit cost and power inputs differ by option.
- Structured ASICs Compete With, And Complement, FPGAs (opens in a new tab), Electronic Design (Dave Bursky), 18 October 2004. Structured ASICs as the middle option, and the crossover volume rising as ASIC NRE rises.
- FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk and Time to Market (opens in a new tab), AMI Semiconductor (Rick Mosher), published by Design and Reuse, 8 June 2006. How NRE, unit cost and time to market compare for FPGAs, structured ASICs and standard-cell ASICs.
- Test Scheme Drops FPGA Cost Below Structured ASICs (opens in a new tab), Electronic Design (Dave Bursky), 29 November 2004. A vendor route that cuts the unit cost of an FPGA for a fixed design, for a small one-off charge: a reminder that the three options are not the only ones.
Where it helps
The lifecycle stages this tool serves: 6 stages in 3 lifecycles.
More cost and business tools
Method notev1Formula, ranges, sources and limits
Compares the total cost of an FPGA, a structured ASIC and a full ASIC at a chosen volume, and finds the volumes where one overtakes another, with and without the cost of a later launch.
Formula
NRE = design engineering + masks and fab set-up + IP and tool licences + test development; discount factor = average over years t = 1 to N of 1 / (1 + r)^t; unit cost = (device price + board cost) x discount factor + energy per unit; device price above the tier = price x tier share; energy per unit = power (W) / 1000 x hours per year x service years x price per kWh; penalty = (months to market − fastest months to market) x lost revenue per month; or (months − fastest months) x revenue per unit x volume / (12 x years); total(V) = NRE + penalty + unit cost x V; cost per unit = total(V) / V; crossover volume = (NRE of the higher-NRE option + its penalty − NRE of the lower-NRE option − its penalty) / (unit cost of the lower-NRE option − unit cost of the higher-NRE option)
| Input | Unit | Range it holds for | Comes from |
|---|---|---|---|
| FPGA: design engineering | USD | from 0 | Your figure |
| FPGA: masks and fab set-up | USD | from 0 | Your figure |
| FPGA: IP and tool licences | USD | from 0 | Your figure |
| FPGA: test development and qualification | USD | from 0 | Your figure |
| FPGA: unit price | USD | from 0 | Editorial estimate (illustrative prices; replace with vendor and foundry quotes). Editorial, as of 2026-10. You can replace it with your own figure. |
| FPGA: volume above which the price drops | units, 0 for none | from 0 | Your figure |
| FPGA: price above that volume | % of the price | 0 to 200 | Your figure |
| FPGA: board cost per unit | USD | from 0 | Your figure |
| FPGA: power per unit | W | 0 to 1000 | Your figure |
| FPGA: time to market | months | 0 to 120 | Your figure |
| Structured ASIC: design engineering | USD | from 0 | Your figure |
| Structured ASIC: masks and fab set-up | USD | from 0 | Your figure |
| Structured ASIC: IP and tool licences | USD | from 0 | Your figure |
| Structured ASIC: test development and qualification | USD | from 0 | Your figure |
| Structured ASIC: unit price | USD | from 0 | Editorial estimate (illustrative prices; replace with vendor and foundry quotes). Editorial, as of 2026-10. You can replace it with your own figure. |
| Structured ASIC: volume above which the price drops | units, 0 for none | from 0 | Your figure |
| Structured ASIC: price above that volume | % of the price | 0 to 200 | Your figure |
| Structured ASIC: board cost per unit | USD | from 0 | Your figure |
| Structured ASIC: power per unit | W | 0 to 1000 | Your figure |
| Structured ASIC: time to market | months | 0 to 120 | Your figure |
| ASIC: design engineering | USD | from 0 | Your figure |
| ASIC: masks and fab set-up | USD | from 0 | Your figure |
| ASIC: IP and tool licences | USD | from 0 | Your figure |
| ASIC: test development and qualification | USD | from 0 | Your figure |
| ASIC unit cost entry | choice | single, parts | Your figure |
| ASIC: unit cost, one figure | USD | from 0 | Editorial estimate (illustrative prices; replace with vendor and foundry quotes). Editorial, as of 2026-10. You can replace it with your own figure. |
| ASIC: die cost | USD | from 0 | Your figure |
| ASIC: package cost | USD | from 0 | Your figure |
| ASIC: test cost per unit | USD | from 0 | Your figure |
| ASIC: volume above which the price drops | units, 0 for none | from 0 | Your figure |
| ASIC: price above that volume | % of the price | 0 to 200 | Your figure |
| ASIC: board cost per unit | USD | from 0 | Your figure |
| ASIC: power per unit | W | 0 to 1000 | Your figure |
| ASIC: time to market | months | 0 to 120 | Your figure |
| Volume entry | choice | annual, lifetime | Your figure |
| Volume per year | units | from 0 | Your figure |
| Product life | years | 1 to 20 | Your figure |
| Lifetime volume | units | from 0 | Your figure |
| Time-to-market penalty basis | choice | month, unit, none | Your figure |
| Lost revenue per month of delay | USD | from 0 | Your figure |
| Revenue per unit | USD | from 0 | Your figure |
| Discount rate | % | 0 to 50 | Your figure |
| Include energy cost | choice | no, yes | Your figure |
| Operating hours per year | hours | 0 to 8760 | Your figure |
| Energy price | USD per kWh | from 0 | Your figure |
| Service life of a unit | years | 0 to 50 | Your figure |
Outputs: FPGA: total cost (USD); Structured ASIC: total cost (USD); ASIC: total cost (USD); Crossover, FPGA and structured ASIC (units); Crossover, structured ASIC and ASIC (units); Crossover, FPGA and ASIC (units).
Assumptions
- All money is in US dollars. Unit prices are per device at the volume entered, and the same price applies to every unit up to the tier.
- An FPGA has a real design cost, because place and route and timing closure take engineering effort, even though it needs no masks.
- The FPGA design is assumed to be moved to the structured ASIC or the ASIC with no change in function, and the one-off cost already includes that conversion.
- The time-to-market penalty counts revenue lost to a later launch against the fastest option. It is not discounted.
- Volume is the lifetime volume; every unit is sold at the unit cost entered. Yield loss and scrap are not modelled: put them in the unit price.
- The preset figures are editorial estimates for typical cases. They are not quotes and not reported prices.
Uncertainty: The arithmetic is exact; the result is only as good as the one-off costs and unit prices entered. Real quotes can differ from typical figures by a factor of two or more, and the crossover moves in proportion.
Known limits
- Real prices depend on the exact device, the node, the quantity and the negotiation. Treat any result as a screening figure and replace the inputs with quotes.
- Technical fit is not priced: the performance, power and area gap between an FPGA and a custom chip, and the risk of a re-spin, decide whether the ASIC can be used at all.
- Respins, redesigns and field updates are not included unless you add them to the NRE. An FPGA can be updated in the field; an ASIC cannot.
- Supply and obsolescence risk, such as the end of life of an FPGA family, are not priced.
- Mask costs change greatly with the node. See the mask set cost estimator (/tools/mask-cost-estimator) for the mask part of the ASIC NRE.
- The chart covers 1,000 to 10 million units. A volume outside that range is still calculated exactly in the totals and crossovers.
Where the method comes from
The Hub's own break-even arithmetic: a straight-line total cost per option with an optional volume tier, a time-to-market penalty measured against the fastest option, and crossovers solved exactly. The option shapes follow the public comparisons named in the sources.
Reference example, checked by test: Worked example in this method note: FPGA NRE $500,000 and $105 a unit with board cost; structured ASIC NRE $2,000,000 and $43 a unit; ASIC NRE $8,000,000 and $23 a unit; 40,000 units a year for 5 years; delays of 0, 4 and 12 months at $50,000 lost revenue a month; no discounting. FPGA: total cost 21,500,000; Structured ASIC: total cost 10,800,000; ASIC: total cost 13,200,000; Crossover, FPGA and structured ASIC 27,419.3; Crossover, structured ASIC and ASIC 320,000; Crossover, FPGA and ASIC 98,780.5.
Versions
- v1 (2026-10-25): First version, built from the tool idea.
Terms on this page
- FPGA
- A chip containing an array of configurable logic blocks, programmable interconnect and embedded memory and DSP resources, whose function is defined after manufacture by loading a configuration bits...
- ASIC
- A chip designed and fabricated for one application or customer rather than sold as a general-purpose part.
- Time to market
- Elapsed time from starting a product to having it available for customers.
- Custom silicon
- A chip developed for a single customer or application rather than for a catalogue, usually with the customer funding the NRE and committing to volume.
- NRE
- One-time development costs for a specific product or customer programme, covering design labour, IP licences, masks, packaging development and test programme creation.
- Fab
- The cleanroom facility where wafers are processed, together with its subfab utilities, chemical distribution and automation.
- IP
- Intellectual property (IP).
- Mask set
- The complete set of photomasks needed to build a design on a process, one or more for each patterned layer.
- Configuration memory
- The memory cells inside an FPGA that hold the loaded bitstream and so define what the device does.
- Die
- A single rectangular block of processed silicon cut from a finished wafer, carrying one complete circuit.
- Bit crossover
- The point at which a new memory generation or cell type overtakes the incumbent in bits shipped, such as DDR5 passing DDR4 or a new NAND node passing its predecessor.
- Place and route
- The physical design steps that put standard cells and macros in legal positions and then connect them with metal wiring that meets timing, power and design rules.
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