Power and thermal estimator
Estimate a chip's dynamic and leakage power from activity, capacitance, voltage and frequency, and its junction temperature from the package and cooling.
Digital and physical designFree to useHow it worksSourcesWhere it helps
Fills the inputs below with typical figures. Replace any of them with your own.
- Junction temperature
- 86.04 degrees C
- 39 K below the 125 degrees C maximum
- Total power
- 29.81 mW
- Leakage is 11.3% of it
- Dynamic power of the blocks
- 6.074 mW
- 5.147 mW switching, 0.5147 mW glitch, 0.4118 mW short-circuit
- Leakage at the junction temperature
- 3.375 mW
- 0.6212 mW at the reference temperature
- IO power
- 8.364 mW
- Power that reaches the maximum
- 1,143 mW
- Without the leakage feedback, from the thermal path alone
- Without leakage feedback
- 85.95 degrees C
- Feedback adds 0.0964 K after 5 steps
- CPU and bus, dynamic5.397 mW18%
- Peripherals, dynamic0.4606 mW2%
- DMA and crypto, dynamic0.2159 mW1%
- Logic leakage2.94 mW10%
- SRAM leakage0.4346 mW1%
- IO8.364 mW28%
- Fixed power12 mW40%
Show the data as a table
| Item | Power (mW) |
|---|---|
| CPU and bus, dynamic | 5.397 mW |
| Peripherals, dynamic | 0.4606 mW |
| DMA and crypto, dynamic | 0.2159 mW |
| Logic leakage | 2.94 mW |
| SRAM leakage | 0.4346 mW |
| IO | 8.364 mW |
| Fixed power | 12 mW |
- With leakage feedback (solid line, circles)
- Leakage held at the reference (dashed line, squares)
- Maximum junction temperature (dotted line, triangles)
Show the data as a table
| Ambient temperature (degrees C) | With leakage feedback | Leakage held at the reference | Maximum junction temperature |
|---|---|---|---|
| -40 | -39.07 | -39.05 | 125 |
| -20 | -19.07 | -19.05 | 125 |
| 0 | 0.9365 | 0.947 | 125 |
| 25 | 25.95 | 25.95 | 125 |
| 45 | 45.96 | 45.95 | 125 |
| 65 | 65.99 | 65.95 | 125 |
| 85 | 86.04 | 85.95 | 125 |
| 105 | 106.1 | 105.9 | 125 |
| 125 | 126.3 | 125.9 | 125 |
- Junction temperature (solid line, circles)
- Maximum junction temperature (dashed line, squares)
Show the data as a table
| Clock frequency (% of the entered values) | Junction temperature | Maximum junction temperature |
|---|---|---|
| 25 | 85.66 | 125 |
| 50 | 85.79 | 125 |
| 75 | 85.92 | 125 |
| 100 | 86.04 | 125 |
| 125 | 86.17 | 125 |
| 150 | 86.3 | 125 |
| 200 | 86.55 | 125 |
Sign in to save your inputs and come back to them later.
| Block | Capacitance (nF) | Switching (mW) | Glitch (mW) | Short-circuit (mW) | Dynamic (mW) | Leakage at Tj (mW) |
|---|---|---|---|---|---|---|
| CPU and bus | 0.21 | 4.574 | 0.4574 | 0.3659 | 5.397 | 1.076 |
| Peripherals | 0.28 | 0.3903 | 0.03903 | 0.03122 | 0.4606 | 1.434 |
| DMA and crypto | 0.084 | 0.183 | 0.0183 | 0.01464 | 0.2159 | 0.4303 |
| Ambient temperature (degrees C) | Junction, with feedback | Junction, leakage held | Total power (mW) |
|---|---|---|---|
| -40 | -39.07 | -39.05 | 26.54 |
| -20 | -19.07 | -19.05 | 26.62 |
| 0 | 0.9365 | 0.947 | 26.76 |
| 25 | 25.95 | 25.95 | 27.07 |
| 45 | 45.96 | 45.95 | 27.55 |
| 65 | 65.99 | 65.95 | 28.37 |
| 85 | 86.04 | 85.95 | 29.81 |
| 105 | 106.1 | 105.9 | 32.33 |
| 125 | 126.3 | 125.9 | 36.74 |
| Frequency (% of entered) | Dynamic (mW) | Total power (mW) | Junction (degrees C) |
|---|---|---|---|
| 25 | 1.518 | 18.95 | 85.66 |
| 50 | 3.037 | 22.57 | 85.79 |
| 75 | 4.555 | 26.19 | 85.92 |
| 100 | 6.074 | 29.81 | 86.04 |
| 125 | 7.592 | 33.43 | 86.17 |
| 150 | 9.11 | 37.05 | 86.3 |
| 200 | 12.15 | 44.3 | 86.55 |
How it works
Chip power splits into dynamic power, which comes from switching capacitance, and leakage, which flows whenever the supply is on and rises steeply with temperature. The power heats the die through the package, and the hotter die leaks more. This tool adds up the power of each block, solves the junction temperature with that feedback, and shows the margin to the limit.
- Dynamic power of each block. Each cycle a switching node charges and discharges its capacitance. A block's power is its activity factor (the share of capacitance that switches each cycle) times its capacitance times the supply voltage squared times its clock frequency. The capacitance is either entered directly or taken as the gate count times the switched capacitance of one gate. Clock gating removes the share of time the block's clock is off.
P switching = alpha x C x V^2 x f x (1 − gated share); C = gate count x C per gate, or entered - Glitch and short-circuit power. Logic nodes also switch on hazards that do no useful work, and during each transition both the pull-up and pull-down networks conduct briefly. Both are taken as a share of the switching power.
P dynamic = P switching x (1 + glitch share + short-circuit share) - Leakage at a reference condition, then scaled. Leakage is given at a reference temperature and the nominal supply, either as a current per gate or as a power density over the die area, and SRAM leakage is given per megabit. Power gating removes a share of the logic leakage. A different supply scales the power as a power of the voltage, and a different temperature scales it by doubling every set number of degrees.
P leak(V, T) = P leak ref x (V / V ref)^m x 2^((T − T ref) / N); per gate: P leak ref = gates x I leak x V ref x (1 − power gated share) - IO and fixed power. Each IO pin charges its load capacitance on a rising edge only, so a pin toggling at a rate f_t (both edges counted) dissipates half of C x V^2 x f_t. Static termination current is multiplied by the IO voltage. Analogue, PLL and other power that does not follow the clocks is entered as a fixed figure.
P IO = pins x 0.5 x C x V io^2 x f toggle + I static x V io - Junction temperature from the package. Four paths are offered. With theta-JA, the junction sits above the ambient by power times theta-JA. From a measured case temperature, theta-JC applies. With a heatsink, the case-to-sink and sink-to-ambient resistances are added in series with theta-JC. When only the top of the package can be measured, psi-JT, which is the temperature rise from the top of the package to the junction per watt, lets you work back to the junction.
Tj = Ta + P x theta-JA; Tj = Tc + P x theta-JC; Tj = Ta + P x (theta-JC + theta-CS + theta-SA); Tj = Tt + P x psi-JT - Feedback between leakage and temperature. Leakage depends on Tj and Tj depends on leakage, so the tool starts at the base temperature and repeats the sum until Tj stops changing. If leakage grows faster than the package can remove the extra heat there is no stable answer, and the tool reports thermal runaway.
Tj(k+1) = T base + theta x (P fixed + P leak(Tj(k)))
Assumptions
- Activity factors, glitch and short-circuit shares, node leakage and capacitance are editorial estimates for a typical library. Replace them with figures from your power analysis or library characterisation.
- Leakage doubles every N degrees with N editable. The scaling is exponential and holds over a moderate range; at very high temperatures it overstates.
- Leakage power scales with a power of the supply voltage (3 by default), an editorial simplification of the combined effect of the voltage on current and on drain-induced barrier lowering.
- The whole die is at one junction temperature. Hot spots in a dense block run hotter than the average.
- Theta-JA, theta-JC and psi-JT are treated as constants. In practice theta-JA changes with airflow, board layout and neighbouring power.
Limits and warnings
- This is a block-level estimate for early planning. Sign-off power comes from a power analysis tool on the netlist and activity from simulation.
- Theta-JC is defined only when nearly all the heat leaves through the case top, as with a heatsink; theta-JA is defined for a standard test board and not for your system. Psi-JT is not a thermal resistance, and it is valid only for a case close to the test condition.
- Dynamic voltage and frequency scaling, power states and workload mix change the power over time; run the tool once for each state that matters.
- Transient heating, thermal capacity and the time to reach the steady state are not modelled.
Sources
The methods and default figures rest on these public sources. The wording here is our own; read the source for its full text.
- Semiconductor and IC Package Thermal Metrics (SPRA953D) (opens in a new tab), Texas Instruments, December 2003, revised March 2024. Definitions of theta-JA, theta-JC and psi-JT and when each applies.
- JESD51-2A: Integrated Circuits Thermal Test Method Environmental Conditions, Natural Convection (Still Air) (opens in a new tab), JEDEC Solid State Technology Association, January 2007, as listed by JEDEC. The standard still-air condition under which theta-JA is measured. It is one of the JESD51 series of thermal test documents.
- CMOS VLSI Design: A Circuits and Systems Perspective, fourth edition (opens in a new tab), Pearson (N. Weste and D. Harris), Fourth edition. The power equation alpha x C x V^2 x f, activity factors, short-circuit and leakage power.
- A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs (opens in a new tab), Design, Automation and Test in Europe (DATE), J. L. Rossello and others, 2005. Static power rises exponentially with temperature, so power and temperature must be solved together.
Where it helps
The lifecycle stages this tool serves: 13 stages in 10 lifecycles.
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Method notev1Formula, ranges, sources and limits
Adds up a chip's dynamic power (alpha x C x V^2 x f with glitch and short-circuit power), leakage scaled for voltage and temperature, SRAM, IO and fixed power, then solves the junction temperature through the package with the feedback between leakage and temperature.
Formula
P switching = alpha x C x V^2 x f x (1 − gated share); C = gate count x C per gate, or entered; P dynamic = P switching x (1 + glitch share + short-circuit share); P leak(V, T) = P leak ref x (V / V ref)^m x 2^((T − T ref) / N); per gate: P leak ref = gates x I leak x V ref x (1 − power gated share); P IO = pins x 0.5 x C x V io^2 x f toggle + I static x V io; Tj = Ta + P x theta-JA; Tj = Tc + P x theta-JC; Tj = Ta + P x (theta-JC + theta-CS + theta-SA); Tj = Tt + P x psi-JT; Tj(k+1) = T base + theta x (P fixed + P leak(Tj(k)))
| Input | Unit | Range it holds for | Comes from |
|---|---|---|---|
| Process node | choice | 180, 130, 90, 65, 40, 28, 16, 7, 5 | Your figure |
| Core voltage | V | 0.4 to 5 | Your figure |
| Switched capacitance per gate | fF | from 0 | Your figure |
| Glitch power | % of switching power | 0 to 60 | Your figure |
| Short-circuit power | % of switching power | 0 to 30 | Your figure |
| Leakage given as | choice | gate, area | Your figure |
| Leakage per gate at the reference | nA | from 0 | Your figure |
| Leakage density at the reference | mW per mm2 | from 0 | Your figure |
| Die area for the leakage density | mm2 | from 0 | Your figure |
| Reference voltage of the leakage figures | V | 0.4 to 5 | Your figure |
| Voltage exponent of leakage power | no unit | 0 to 8 | Your figure |
| Reference temperature of the leakage figures | degrees C | -55 to 150 | Your figure |
| Degrees for leakage to double | degrees | 8 to 60 | Your figure |
| Logic leakage removed by power gating | % | 0 to 100 | Your figure |
| Leakage follows junction temperature | choice | yes, no | Your figure |
| SRAM | Mbit | from 0 | Your figure |
| SRAM leakage at the reference | uW per Mbit | from 0 | Your figure |
| Switching IO pins | pins | from 0 | Your figure |
| Load per IO pin | pF | from 0 | Your figure |
| IO voltage | V | 0.4 to 5 | Your figure |
| IO toggle rate, both edges | MHz | from 0 | Your figure |
| Static IO and termination current | mA | from 0 | Your figure |
| Fixed power: analogue, PLL and similar | mW | from 0 | Your figure |
| Thermal path | choice | ja, jc, sink, psijt | Your figure |
| Theta-JA | K/W | from 0 | Your figure |
| Theta-JC | K/W | from 0 | Your figure |
| Theta-CS | K/W | from 0 | Your figure |
| Theta-SA | K/W | from 0 | Your figure |
| Psi-JT | K/W | 0 to 5 | Your figure |
| Ambient temperature | degrees C | -55 to 150 | Your figure |
| Case temperature | degrees C | -55 to 175 | Your figure |
| Case-top temperature | degrees C | -55 to 175 | Your figure |
| Maximum junction temperature | degrees C | 60 to 200 | Your figure |
| Temperature unit | choice | C, K | Your figure |
| Power unit | choice | mW, W | Your figure |
Outputs: Dynamic power of the blocks (W); Leakage at the junction temperature (W); Total power (W); Junction temperature (degrees C); Margin to the maximum junction temperature (K).
Assumptions
- Activity factors, glitch and short-circuit shares, node leakage and capacitance are editorial estimates for a typical library. Replace them with figures from your power analysis or library characterisation.
- Leakage doubles every N degrees with N editable. The scaling is exponential and holds over a moderate range; at very high temperatures it overstates.
- Leakage power scales with a power of the supply voltage (3 by default), an editorial simplification of the combined effect of the voltage on current and on drain-induced barrier lowering.
- The whole die is at one junction temperature. Hot spots in a dense block run hotter than the average.
- Theta-JA, theta-JC and psi-JT are treated as constants. In practice theta-JA changes with airflow, board layout and neighbouring power.
Uncertainty: The arithmetic is exact. The power is as good as the activity, capacitance and leakage entered, which are editorial here, and block-level estimates differ from sign-off power analysis by tens of per cent. The junction temperature also depends on the thermal resistance, which varies with the board and the airflow.
Known limits
- This is a block-level estimate for early planning. Sign-off power comes from a power analysis tool on the netlist and activity from simulation.
- Theta-JC is defined only when nearly all the heat leaves through the case top, as with a heatsink; theta-JA is defined for a standard test board and not for your system. Psi-JT is not a thermal resistance, and it is valid only for a case close to the test condition.
- Dynamic voltage and frequency scaling, power states and workload mix change the power over time; run the tool once for each state that matters.
- Transient heating, thermal capacity and the time to reach the steady state are not modelled.
Where the method comes from
The Hub's own block-level power and thermal arithmetic: the standard switching power equation, exponential leakage scaling and the JESD51 style junction-to-ambient, junction-to-case and psi-JT relationships, solved together by iteration.
Reference example, checked by test: Worked example in this method note: the microcontroller preset (three blocks at 40 nm and 1.1 V, 4 Mbit of SRAM, 48 IO pins, 12 mW fixed power, theta-JA 35 K/W at 85 degrees C), hand-worked in the tool's unit test. Dynamic power of the blocks 0.006074; Leakage at the junction temperature 0.003375; Total power 0.029812; Junction temperature 86.0434; Margin to the maximum junction temperature 38.9566.
Versions
- v1 (2026-10-25): First version, built from the tool idea.
Terms on this page
- Chip
- The everyday word for a finished integrated circuit, used loosely for both the bare die and the packaged part sold to a customer.
- Leakage power
- Power drawn by transistors that are nominally off, through subthreshold conduction and gate tunnelling.
- Junction temperature
- The temperature of the active silicon itself, as opposed to the case, board or ambient.
- Dynamic power
- Power consumed by charging and discharging capacitance when nodes switch, plus short-circuit current during transitions.
- Die
- A single rectangular block of processed silicon cut from a finished wafer, carrying one complete circuit.
- Clock gating
- A power-saving technique that inserts an enable-controlled latch and AND gate so a register bank's clock stops toggling when its data will not change.
- Glitch
- A transient voltage excursion on a quiet net caused by a switching aggressor.
- Power density
- Output power divided by converter volume or weight, quoted in watts per cubic inch or kilowatts per litre.
- Die size
- The physical area of a single chip on the wafer, set by whichever dominates: total logic and memory area, IO and bump count, or analogue and power structures.
- SRAM
- A volatile memory that holds each bit in a cross-coupled inverter latch, keeping its value as long as power is applied and needing no refresh.
- Power gating
- Cutting supply to an idle block using header or footer switch cells so that its leakage falls to near zero, at the cost of state loss, wake-up latency and inrush current when the block is restored.
- I/O
- Input/output (I/O): the signals, pins and circuits through which a chip exchanges data with the outside world, together with their electrical standards.
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