PDK release maturity checklist
Track a process design kit's decks, models, libraries and documents against each release stage, and see readiness per stage and what blocks the next one.
Quality worksheetsFor membersHow it worksSourcesWhere it helps
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How it works
A process design kit (PDK) is not released all at once. Decks, models, views and documents arrive in drafts and are finished over several releases. This checklist lists the items of a kit, says from which release stage each is needed and by which stage it must be final, tracks their status, and shows how ready the kit is at each stage and what blocks the next one.
- Set the stages. The checklist uses four release stages written in our own words: 0.1 early engineering (tools can be set up and test layouts tried), 0.5 design-ready (decks run end to end, models have corners, IP and test chips can be designed with known risk), 0.9 release candidate (decks and views final, models fitted to early silicon) and 1.0 production (everything final, correlated with silicon and signed off). Foundries number and gate their releases in their own ways, so rename the stages in your notes if yours differ.
- Propose the items. The proposal lists what a kit usually holds: DRC, LVS, antenna and fill decks, parasitic extraction and its corners, device models (typical, corner, statistical and mismatch, ageing; passive, RF and noise models for a mixed-signal process), symbols, schematic views and parameterised cells, technology files for the tools, the design rule manual and user guide, reliability and ESD rules, DFM recommendations, quality and validation reports, test chip correlation and release notes. Each item gets the stage from which it is needed and the stage by which it must be final; this is our typical mapping, and every row can be changed or marked not needed.
- Track the status. Each item is missing, preliminary or final, with a version and an owner. An item that is due but not yet final needs to be at least preliminary; an item that must be final at a stage needs to be final.
- Measure readiness at each stage. An item is due at a stage when its first-needed stage is that stage or earlier. It is in the needed state when it is final if its final-by stage has been reached, and at least preliminary otherwise. Readiness is the share of due items in the needed state.
readiness at stage S = items in the needed state / items due by S - Find the blockers. The blockers for a stage are the due items that are not in the needed state, listed with the state needed, the state now and the owner. The highest stage ready is the last one for which that stage and every earlier one has no blockers.
Assumptions
- The stage definitions and the mapping of items to stages are the Hub's own typical judgement, not a published scheme; foundries and customers agree their own.
- Cumulative stages: an item due at 0.5 is still due at 0.9 and 1.0, and each later stage asks for more of it to be final.
- Status is the checker's honest call: final means reviewed, versioned and released with the kit, not just present.
- The example sheets are invented.
Limits and warnings
- The checklist does not run any deck or open any model; it records the status you give each item.
- A kit has many more files than the 35 or so items listed. Split an item into rows when you need to track it more finely, for example one row for each EDA tool's DRC deck.
- Some processes need items not listed (embedded memory, photonics, power devices, special masks); add them as rows.
- Open and academic kits use their own version schemes, which do not map one to one onto these stages.
Sources
The methods and default figures rest on these public sources. The wording here is our own; read the source for its full text.
- Versioning Information, SkyWater Open Source PDK documentation (opens in a new tab), SkyWater and Google, hosted on Read the Docs, undated page, checked October 2026. A public example of tying a PDK version to maturity: alpha, beta (qualification tested) and production (verified on hardware). Our four stages are a different scheme; this is context, not the source of the mapping.
- FSA Introduces Mixed-Signal/RF PDK Checklist Version 2.0 (opens in a new tab), Design And Reuse, announcing the Fabless Semiconductor Association checklist, 18 July 2006. Confirms that an industry checklist of what a PDK should contain has been used with foundry kits, including a SPICE model checklist for correlation with silicon. The items here are our own list.
- Taming The PDK Beast At DAC (Steve Schulz, Si2) (opens in a new tab), Semiconductor Engineering, 19 May 2014. The Si2 OpenPDK Coalition's case for one source for all PDK data and open standards (Open Process Specification, OpenPCells); background on what a kit has to carry.
- Si2 OpenStandards, OpenPDK Coalition (opens in a new tab), Silicon Integration Initiative (Si2), undated page, checked October 2026. The coalition's aim of a PDK built once and translated into each EDA tool and foundry format. The coalition is archived.
Where it helps
The lifecycle stages this tool serves: 5 stages in 2 lifecycles.
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Terms on this page
- PDK
- The foundry-supplied package that makes a process usable by EDA tools.
- IP
- Intellectual property (IP).
- Silicon
- The group IV element that carries almost all commercial semiconductor volume, valued for its abundance, its stable native oxide and a manufacturing base refined over sixty years.
- DRC
- Physical verification that compares a layout against the foundry's geometric rule deck for widths, spacings, enclosures, densities and antenna ratios.
- LVS
- Physical verification that extracts a netlist from the drawn layout and compares its devices and connectivity against the reference schematic or CDL netlist.
- Parasitic extraction
- Deriving the resistance and capacitance of every wire and via from routed layout geometry and the process stack, producing an annotated network for timing, noise and power analysis.
- RF
- Radio frequency (RF): the range of electromagnetic frequencies used for wireless communication and radar, roughly from a few kilohertz to hundreds of gigahertz.
- DRM
- The foundry document that specifies the geometric and electrical rules a layout must obey for a given process, such as minimum widths, spacings, enclosures, density windows and antenna ratios.
- ESD
- A rapid transfer of static charge into or out of a device, delivering nanosecond to microsecond current pulses that can rupture gate dielectrics, melt junctions or fuse metal.
- DFM
- The practice of shaping layout beyond minimum legal rules so that it prints and yields reliably, using recommended rules, via doubling, wire spreading and litho-friendly patterning.
- Test chip
- A chip made to prove designs, IP blocks or process features in silicon rather than to be sold.
- Release notes
- The document issued with a release of software, firmware, IP or a design kit that states what it contains, what changed since the previous version, known issues and limits, and any action users mus...
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