Hard IP port effort estimator

How it works

Porting a hard macro (an analog block, a PHY, a memory, a standard cell library) to another process or metal stack costs anything from a small fraction of a new design to as much as one. This tool prices it with a parametric effort model: a base effort from the macro's size and content mix, scaled by the kind of change, how similar the design rules are, the team's experience and whether a migration tool is available, plus the fixed costs of characterisation, a test chip and qualification. Every factor is a Hub editorial estimate that you should replace with your own project history.

1. Set the base effort of a new design. Each content type has an effort rate in engineer-weeks per mm2 for building it from scratch: custom analog, custom digital, compiled memory and standard cell digital. The base is the size times the mix-weighted rate. A library priced by cell count uses engineer-weeks per cell instead of the standard cell area share.base = area x (analog share x analog rate + custom digital share x custom digital rate + memory share x memory rate + standard cell share x standard cell rate) + cells x rate per cell
2. Split it into activities. The base is divided between circuit work (schematic and pre-layout simulation), layout, and verification with views and documentation. The default split is 28%, 40% and 32%.activity base = base x activity split
3. Scale for the change. The kind of change decides how much of each activity is repeated: a new node repeats most of it, a metal stack change or a PDK version change very little. The design rule similarity, the team's experience and the migration tool then scale it. A migration tool helps the circuit and layout activities only; it does not help verification.activity effort = activity base x change factor x similarity factor x skill factor x tool factor (circuit and layout only)
4. Add characterisation. Characterisation scales with the number of corners. Each corner has a fixed cost plus a cost per mm2 for each content type, or per cell for a library, then the change-type factor.characterisation = corners x (fixed + area x sum of share x rate per mm2 + cells x rate per cell) x change factor
5. Add the fixed items. A test chip adds design and bring-up effort, and its shuttle cost. Qualification adds effort and a cost. A migration tool adds set-up effort. Project management is a percentage of everything, and contingency a percentage of that.total = (activities + characterisation + test chip + qualification + tool set-up) x (1 + project management) x (1 + contingency)
6. Make the schedule and cost. The design and characterisation phases are shared across the team at the stated efficiency. Characterisation runs while the test chip is in fabrication, bring-up is limited to three people, and qualification takes a fixed time. Cost is engineer-weeks times the loaded rate plus the EDA and compute rate, plus the shuttle and qualification costs.design weeks = effort / (team x efficiency); schedule = design + max(characterisation, fabrication) + bring-up + qualification, all x (1 + contingency)
7. Test the similarity. The sensitivity view repeats the whole estimate at high, medium and low design rule similarity, and the chart sweeps the similarity factor, because similarity is the least certain input at the start of a port.same model with the similarity factor set to 0.75, 1 and 1.2

Sources

The methods and default figures rest on these public sources. The wording here is our own; read the source for its full text.

• Analog Migration Equals Redesign (opens in a new tab), Semiconductor Engineering (Ann Mutschler), 24 May 2018. Why analog migration across nodes is far harder than digital reuse, and why FinFET effects push teams to redesign.
• Accelerating Analog Design Migration (opens in a new tab), Synopsys blog (Yuval Shay), first published in Semiconductor Engineering, 12 October 2023. The migration steps and why layout migration and simulation are harder than schematic migration.
• Reuse of Analog Mixed Signal IP for SoC Design: Progress Report (opens in a new tab), Cadence Design Systems (Tim Henricks), published on Design and Reuse, 8 November 2004. Tool-assisted porting that took about as much effort as laying out from scratch; it pays off for many similar blocks.