Logic density estimator
Estimate standard cell logic density from contacted gate pitch, metal pitch, cell height and design utilisation, and compare nodes on a common basis.
Digital and physical designFree to useHow it worksSourcesWhere it helps
Fills the inputs below with typical figures. Replace any of them with your own.
- Weighted transistor density
- 138.2 MTr/mm2
- Bohr weighted, 60% NAND2; 1.48 transistors per gate pitch per cell height
- NAND2 cell area
- 32,130 nm2
- 3 gate pitches wide, 210 nm tall
- Gates per mm2, raw
- 31.12 million
- NAND2 equivalents before utilisation
- Achievable density
- 87.06 MTr/mm2
- After 70% utilisation and 10% overhead
- Achievable gates per mm2
- 19.61 million
| Cell | Transistors | Width (gate pitches) | Area (nm2) | Density (MTr/mm2) |
|---|---|---|---|---|
| NAND2 | 4 | 3 | 32,130 | 124.5 |
| Scan flip-flop | 34 | 20 | 214,200 | 158.7 |
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Bohr weighted, 60% NAND2. Each node uses its own pitches and height; the cell counts, utilisation and overhead are the ones entered above. Figures marked as estimates in the table are not foundry data.
- TSMC N16 (16FF)24.07 MTr/mm215.2 achievable
- TSMC N7108.2 MTr/mm268.2 achievable
- TSMC N5138.2 MTr/mm287.1 achievable
- TSMC N3192.3 MTr/mm2121 achievable
- Intel 7 (high-performance cell)60.46 MTr/mm238.1 achievable
- Intel 4 (high-performance cell)123.3 MTr/mm277.7 achievable
- Generic 3 nm gate-all-around class (Hub estimate)126.4 MTr/mm279.6 achievable
- Intel 10 nm (2017, the reference case)100.8 MTr/mm263.5 achievable
Show the data as a table
| Item | Density (MTr/mm2) |
|---|---|
| TSMC N16 (16FF) | 24.07 MTr/mm2 |
| TSMC N7 | 108.2 MTr/mm2 |
| TSMC N5 | 138.2 MTr/mm2 |
| TSMC N3 | 192.3 MTr/mm2 |
| Intel 7 (high-performance cell) | 60.46 MTr/mm2 |
| Intel 4 (high-performance cell) | 123.3 MTr/mm2 |
| Generic 3 nm gate-all-around class (Hub estimate) | 126.4 MTr/mm2 |
| Intel 10 nm (2017, the reference case) | 100.8 MTr/mm2 |
| Node | CPP (nm) | MMP (nm) | Cell height (nm) | Tracks | NAND2 area (nm2) | Density (MTr/mm2) | Achievable (MTr/mm2) | Achievable (million gates/mm2) | What is reported and what is assumed |
|---|---|---|---|---|---|---|---|---|---|
| TSMC N16 (16FF) | 90 | 64 | 576 | 9 | 207,360 | 24.07 | 15.16 | 3.038 | CPP 90 nm and 1x metal pitch 64 nm are TSMC's IEDM 2014 values as reported by Chipworks. The 9-track height (9 x 64 nm) and the double diffusion break are the Hub's assumptions. |
| TSMC N7 | 57 | 40 | 240 | 6 | 41,040 | 108.2 | 68.16 | 15.35 | 2-fin cell with 57 nm CPP, 40 nm metal pitch and 240 nm height, as reported by Angstronomics (June 2022). Angstronomics' own density for this cell is lower than this metric gives; pitches do not capture everything. Single diffusion break assumed. |
| TSMC N5 | 51 | 28 | 210 | 7.5 | 32,130 | 138.2 | 87.06 | 19.61 | 2-fin cell with 51 nm CPP, 28 nm M0 pitch and 210 nm height, as reported by Angstronomics (June 2022), whose measured density of 137.6 MTr/mm2 on a shipping chip is within 1% of this metric. Single diffusion break assumed. |
| TSMC N3 | 45 | 23 | 171 | 7.43 | 23,085 | 192.3 | 121.2 | 27.29 | CPP 45 nm is from TSMC's IEDM 2022 N3 paper and 23 nm metal pitch from its N3E paper, both as reported by Scotten Jones (January 2023). The 171 nm height for a 2-2 FinFlex cell is the Hub's derivation from his 1.39x density against N5 2-2 cells, not a reported figure. |
| Intel 7 (high-performance cell) | 60 | 40 | 408 | 10.2 | 73,440 | 60.46 | 38.09 | 8.578 | CPP 60 nm and the 408 nm high-performance cell are from Scotten Jones's Intel 4 Deep Dive (June 2022). The 40 nm M0 pitch is the Hub's estimate; it only sets the track count shown. A 272 nm high-density cell exists but was not used. |
| Intel 4 (high-performance cell) | 50 | 30 | 240 | 8 | 36,000 | 123.3 | 77.7 | 17.5 | CPP 50 nm, 30 nm minimum metal pitch and the 240 nm high-performance cell, as reported by Scotten Jones (June 2022) from Intel's VLSI 2022 paper. Intel 4 offers no high-density cell. |
| Generic 3 nm gate-all-around class (Hub estimate) | 48 | 34 | 244 | 7.18 | 35,136 | 126.4 | 79.61 | 17.93 | A Hub estimate for a 3 nm gate-all-around node, not any foundry's published figures: no foundry pitches for such a node were found in a public source. The 48 nm gate pitch is the 3 nm class value of roadmap tables. The 244 nm height is the Hub's derivation: it gives a density 1.19 times a Samsung 5 nm that is 1/1.30 of TSMC N5, the ratios Scotten Jones reports (January 2023). The 34 nm metal pitch is a guess and only sets the track count shown. Replace all three with TechInsights or foundry data. |
| Intel 10 nm (2017, the reference case) | 54 | 36 | 272 | 7.56 | 44,064 | 100.8 | 63.48 | 14.3 | CPP 54 nm, 36 nm minimum metal pitch and 272 nm cell height from Intel's Technology and Manufacturing Day slides (March 2017). Intel reported 100.8 MTr/mm2; this tool's defaults give 100.76. |
- Gate pitch 10% tighter (45.9 nm) (solid line, circles)
- Gate pitch 51 nm (dashed line, squares)
- Gate pitch 10% looser (56.1 nm) (dotted line, triangles)
Show the data as a table
| Cell height (tracks) | Gate pitch 10% tighter (45.9 nm) | Gate pitch 51 nm | Gate pitch 10% looser (56.1 nm) |
|---|---|---|---|
| 5 | 230.3 | 207.3 | 188.4 |
| 5.5 | 209.4 | 188.4 | 171.3 |
| 6 | 191.9 | 172.7 | 157 |
| 6.5 | 177.2 | 159.4 | 145 |
| 7 | 164.5 | 148.1 | 134.6 |
| 7.5 | 153.5 | 138.2 | 125.6 |
| 8 | 143.9 | 129.6 | 117.8 |
| 9 | 128 | 115.2 | 104.7 |
| 10 | 115.2 | 103.6 | 94.22 |
| Tracks | Gate pitch 10% tighter (45.9 nm) | Gate pitch 51 nm | Gate pitch 10% looser (56.1 nm) |
|---|---|---|---|
| 5 | 230.3 | 207.3 | 188.4 |
| 5.5 | 209.4 | 188.4 | 171.3 |
| 6 | 191.9 | 172.7 | 157 |
| 6.5 | 177.2 | 159.4 | 145 |
| 7 | 164.5 | 148.1 | 134.6 |
| 7.5 | 153.5 | 138.2 | 125.6 |
| 8 | 143.9 | 129.6 | 117.8 |
| 9 | 128 | 115.2 | 104.7 |
| 10 | 115.2 | 103.6 | 94.22 |
How it works
Logic density is how many transistors a process packs into a square millimetre of standard-cell logic. Node names no longer tell you, so process engineers compare nodes by their pitches. This tool turns the contacted gate pitch, the metal pitch and the cell height into the weighted transistor density that Intel's Mark Bohr proposed in 2017, then applies placement utilisation and overhead to give the density a real block can reach.
- Find the cell height. The standard-cell library height is either entered in nm, or built from a track count and the pitch of one routing track. Tracks are counted on the metal pitch unless you give a track pitch, because some processes count tracks on the second metal layer.
cell height = tracks x track pitch (or the nm height as entered) - Size the two reference cells. The metric uses a two-input NAND (4 transistors) and a scan flip-flop. A cell is as wide as its logic gates plus the dummy gates at its borders: one with a single diffusion break, two with a double break. The gate counts default to 2 for the NAND and 19 for the flip-flop, and the flip-flop to 34 transistors.
cell width = (logic gates + dummy gates) x CPP; cell area = width x cell height - Weigh the two densities. Each cell's density is its transistor count over its area. The weighted density mixes the small NAND and the large flip-flop, 60% and 40% in Bohr's proposal, to stand for the spread of cell sizes in real logic. The default flip-flop figures were fitted so that Intel's published 10 nm inputs give the density Intel reported (100.8 MTr/mm2 against 100.76 here); the weights are Bohr's, the cell counts are the Hub's.
density (MTr/mm2) = 1e6 x (0.6 x NAND2 transistors / NAND2 area + 0.4 x flip-flop transistors / flip-flop area), areas in nm2 - Compare libraries with one number. Dividing the density by one over the gate pitch times the cell height gives transistors per gate pitch per cell height. For a single diffusion break and these defaults it is 1.48, the figure used in public density estimates. Use it to compare libraries with different pitches.
k = density x CPP x cell height / 1e6 - Count gates. A gate is one NAND2 equivalent. Raw gates per mm2 is the area of a square millimetre over the NAND2 area. The weighted transistor density is a library figure for the two reference cells, not the density of a chip.
gates per mm2 = 1e12 / NAND2 area in nm2 - Apply utilisation and overhead. Placed cells never fill a block. Placement utilisation is the share of the core taken by cells, and overhead covers the power grid, clock tree, macro halos and filler outside it. The achievable density is the library figure times both.
achievable density = density x utilisation x (1 − overhead); block area = gates / achievable gates per mm2
Assumptions
- Pitches and cell heights are those reported or estimated in public sources, each named in the preset note. The Hub's own arithmetic or assumptions are marked as such. No foundry publishes this metric.
- A NAND2 has 4 transistors and 2 logic gates; a scan flip-flop 34 transistors and 19 logic gates. These are the Hub's fitted defaults: Bohr's proposal fixes the weights and the two cell types, but his public material does not list the transistor and gate counts used here.
- The same cell height is used for both reference cells. Libraries with double-height flip-flops or multi-height cells need different areas.
- Fins or nanosheets per device are shown for reference only. The cell height already reflects them.
Limits and warnings
- The metric is a library figure, not the density of a chip. Real chips mix SRAM, analog, I/O and wiring-limited logic, and shipping products reach a fraction of it.
- Pitches do not capture everything: fin depopulation, contact over active gate, buried power rails, backside power and cell architecture all change area at the same pitches. Treat two nodes within 15% of each other as level.
- Where a pitch is an estimate, a small error moves the density in proportion: a 5% error in the cell height is a 5% error in the density.
- SRAM bit cells scale differently from logic and are not part of this metric; compare them separately.
Sources
The methods and default figures rest on these public sources. The wording here is our own; read the source for its full text.
- 10 nm technology leadership (Technology and Manufacturing Day slides, K. Mistry) (opens in a new tab), Intel, March 2017. Intel 10 nm gate pitch 54 nm, minimum metal pitch 36 nm, cell height 272 nm, single dummy gate; the 0.6 and 0.4 weighting graphic.
- Intel Now Packs 100 Million Transistors in Each Square Millimeter (opens in a new tab), IEEE Spectrum (Rachel Courtland), 30 March 2017. Mark Bohr's density metric from a standard NAND2 cell and a scan flip-flop cell; 100.8 MTr/mm2 at 10 nm.
- The TRUTH of TSMC 5nm (opens in a new tab), Angstronomics (SkyJuice), 25 June 2022. TSMC N7 and N5 gate pitch, metal pitch and cell height; measured N5 chip density.
- IEDM 2022: TSMC 3nm (opens in a new tab), SemiWiki (Scotten Jones), 2 January 2023. TSMC N3 gate pitch of 45 nm, N3E metal pitch of 23 nm and the FinFlex density ratios.
- Intel 4 Deep Dive (opens in a new tab), SemiWiki (Scotten Jones), 13 June 2022. Intel 7 and Intel 4 gate pitch and high-performance cell height.
- IEDM: Monday was FinFET Day (opens in a new tab), Chipworks (Dick James), 18 December 2014. TSMC 16 nm gate pitch 90 nm and 1x metal pitch 64 nm.
- International Roadmap for Devices and Systems, 2021 Update: More Moore, Table MM-7 (opens in a new tab), IEEE IRDS, 2021. The ground rule roadmap for logic, written in gate pitch and metal pitch, and the text on cell height scaling.
Where it helps
The lifecycle stages this tool serves: 2 stages in 1 lifecycle.
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Method notev1Formula, ranges, sources and limits
Estimates standard-cell logic density from contacted gate pitch, metal pitch and cell height with Bohr's weighted NAND2 and scan flip-flop metric, then the gates per mm2 and the density a placed block can reach after utilisation and overhead.
Formula
cell height = tracks x track pitch (or the nm height as entered); cell width = (logic gates + dummy gates) x CPP; cell area = width x cell height; density (MTr/mm2) = 1e6 x (0.6 x NAND2 transistors / NAND2 area + 0.4 x flip-flop transistors / flip-flop area), areas in nm2; k = density x CPP x cell height / 1e6; gates per mm2 = 1e12 / NAND2 area in nm2; achievable density = density x utilisation x (1 − overhead); block area = gates / achievable gates per mm2
| Input | Unit | Range it holds for | Comes from |
|---|---|---|---|
| Node preset | choice | custom, tsmc-n16, tsmc-n7, tsmc-n5, tsmc-n3, intel-7, intel-4, samsung-3gae, intel-10 | Your figure |
| Cell height given as | choice | nm, tracks | Your figure |
| Contacted gate pitch | nm | 10 to 200 | Your figure |
| Minimum metal pitch | nm | 8 to 200 | Your figure |
| Cell height | nm | 50 to 1000 | Your figure |
| Cell height in tracks | tracks | 3 to 14 | Your figure |
| Track pitch, 0 for the metal pitch | nm | 0 to 200 | Your figure |
| Fins or nanosheets per device (shown only) | count | 0 to 10 | Your figure |
| Dummy gates at a cell border | choice | 1, 2 | Your figure |
| NAND2 transistors | count | 2 to 12 | Your figure |
| NAND2 logic gates in width | gates | 1 to 6 | Your figure |
| Scan flip-flop transistors | count | 10 to 80 | Your figure |
| Scan flip-flop logic gates in width | gates | 6 to 40 | Your figure |
| NAND2 weight | % | 0 to 100 | Your figure |
| Density metric | choice | bohr, nand2 | Your figure |
| Placement utilisation | % | 20 to 100 | Your figure |
| Overhead outside the placed cells | % | 0 to 60 | Your figure |
| Design size, 0 to skip | million NAND2 gates | from 0 | Your figure |
Outputs: Weighted transistor density (MTr/mm2); NAND2 cell area (nm2); NAND2 gates per mm2 before utilisation (million gates/mm2); Achievable density after utilisation and overhead (MTr/mm2); Achievable gates per mm2 (million gates/mm2).
Assumptions
- Pitches and cell heights are those reported or estimated in public sources, each named in the preset note. The Hub's own arithmetic or assumptions are marked as such. No foundry publishes this metric.
- A NAND2 has 4 transistors and 2 logic gates; a scan flip-flop 34 transistors and 19 logic gates. These are the Hub's fitted defaults: Bohr's proposal fixes the weights and the two cell types, but his public material does not list the transistor and gate counts used here.
- The same cell height is used for both reference cells. Libraries with double-height flip-flops or multi-height cells need different areas.
- Fins or nanosheets per device are shown for reference only. The cell height already reflects them.
Uncertainty: The arithmetic is exact. The result is as good as the pitches and the cell counts: Public pitch figures named in the method note; the cell counts are the Hub's fitted defaults. Expect real libraries to differ from the metric by 10 to 20%.
Known limits
- The metric is a library figure, not the density of a chip. Real chips mix SRAM, analog, I/O and wiring-limited logic, and shipping products reach a fraction of it.
- Pitches do not capture everything: fin depopulation, contact over active gate, buried power rails, backside power and cell architecture all change area at the same pitches. Treat two nodes within 15% of each other as level.
- Where a pitch is an estimate, a small error moves the density in proportion: a 5% error in the cell height is a 5% error in the density.
- SRAM bit cells scale differently from logic and are not part of this metric; compare them separately.
Where the method comes from
Follows Bohr, logic transistor density metric, as presented by Intel at Technology and Manufacturing Day (March 2017) (opens in a new tab). The platform's version departs from it as follows.
- The NAND2 and scan flip-flop cells are sized from the gate pitch, the cell height and a count of logic and dummy gates Why: Intel's metric uses its own library cell areas, which are not public; the gate counts are fitted so the published Intel 10 nm inputs give its reported density.
- Utilisation and overhead are applied to turn the library figure into an achievable block density Why: The metric describes the process; a designer needs the density a placed and routed block reaches.
Reference example, checked by test: Intel 10 nm inputs from Intel's Technology and Manufacturing Day slides (March 2017): CPP 54 nm, metal pitch 36 nm, cell height 272 nm, single dummy gate. Intel reported 100.8 MTr/mm2; the hand-worked value is 100.7625. Utilisation 70% and overhead 10% are the Hub's defaults. Weighted transistor density 100.763; NAND2 cell area 44,064; NAND2 gates per mm2 before utilisation 22.6943; Achievable density after utilisation and overhead 63.4804; Achievable gates per mm2 14.2974.
Versions
- v1 (2026-10-25): First version, built from the tool idea.
Terms on this page
- Standard cell
- A small, pre-designed logic cell, such as a gate, flip-flop or buffer, with a fixed height so that cells can be placed in rows and connected automatically.
- CPP
- The centre-to-centre distance between adjacent transistor gates including the contact between them, the fundamental horizontal scaling dimension in the front end.
- Cell height
- The vertical size of a standard cell, usually quoted in routing tracks, for example a 6-track or 5-track library.
- Utilisation
- The fraction of available placeable core area consumed by cell and macro instances, typically quoted as a percentage.
- Transistor
- A three-terminal semiconductor device in which a signal on one terminal controls current flow between the other two, giving switching or amplification.
- Transistor density
- The number of transistors that fit in a square millimetre, usually quoted in millions of transistors per mm2.
- Standard cell library
- A characterised collection of small fixed-height logic cells, flip-flops and buffers designed to abut in rows and be assembled automatically by synthesis and place and route.
- Nanometre
- One billionth of a metre, the length scale of modern transistor features.
- Routing track
- One of the evenly spaced lines on a metal layer along which the router may draw a wire, set by that layer's pitch.
- NAND flash
- Non-volatile memory whose cells are wired in series strings, trading random access for very high density and low cost per bit.
- Scan flip-flop
- A flip-flop with a multiplexer on its data input that selects between the functional path and the scan input from the previous cell in the chain.
- Diffusion
- The thermally driven spreading of dopant atoms through silicon.
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