Memory bit cost estimator

How it works

The price of memory is quoted per bit, so the question is how many good bits one wafer yields and what that wafer costs. This tool turns a wafer cost, a die size, a density and a yield into cost per gigabit and per gigabyte for DRAM or 3D NAND, with the test and assembly cost added, and shows how the answer moves with yield and, for NAND, with the number of layers.

1. Find the die size. Enter the die area, or its width and height. Or let the tool build it up: DRAM from the cell area and the array efficiency, NAND from the memory-hole footprint, the layer count and the bits per cell. Array efficiency is the share of the die that is memory array rather than periphery.DRAM die area = bits x cell area / array efficiency; NAND die area = bits / (layers x bits per cell) x hole footprint / array efficiency; bits = gigabits x 1,073,741,824
2. Count the die on the wafer. The scribe lane is added to each side of the die, and the standard rectangular-die approximation shared with the die-per-wafer tool gives the gross count on a 300 mm wafer.gross die = floor(pi x (D/2)^2 / A − pi x D / sqrt(2 x A)), with D = 300 − 2 x edge exclusion and A = (width + scribe) x (height + scribe)
3. Find the yield. Enter a yield, or compute it from defect density and die area. Poisson treats defects as random and independent; Murphy softens that for clustering; the negative binomial model has a clustering factor. Redundant rows, columns and blocks then rescue a share of the faulty die.Poisson: Y = e^(−A x D0); Murphy: Y = ((1 − e^(−A x D0)) / (A x D0))^2; negative binomial: Y = (1 + A x D0 / alpha)^(−alpha); with repair: Y' = Y + (1 − Y) x repair share; A in cm2
4. Cost the good die. Probe test is paid on every gross die, assembly and final test on every good die. Spare blocks, parity and over-provisioning hold back some capacity that is never sold.good die = gross die x Y'; cost per good die = (wafer cost + probe cost x gross die) / good die + assembly cost; sellable gigabits = density x (1 − spare share)
5. Express it per bit. Cost per gigabit is the cost of a good die over its sellable gigabits. A gigabyte is eight gigabits.cost per Gbit = cost per good die / sellable Gbit; cost per GB = 8 x cost per Gbit; bit density = density / die area
6. Sweep yield and layers. The yield table holds everything else fixed and varies only the yield. For NAND the layer sweep keeps the capacity, the cell footprint and the bits per cell. With CMOS under the array the whole die shrinks as layers are added; without it the periphery stays the same size. The wafer cost rises by your slope for every 10 layers added. For DRAM the sweep varies the die area at the same density.NAND die area at L layers = array area x (L0 / L) / array efficiency (CMOS under array), or array area x (L0 / L) + periphery (otherwise)

Sources

The methods and default figures rest on these public sources. The wording here is our own; read the source for its full text.

• Micron 1α DRAM Technology (opens in a new tab), TechInsights, Undated web article, 2021. Micron 1-alpha 8 Gbit DDR4 die: 25.41 square millimetres, 0.315 Gbit per square millimetre.
• SK Hynix D1a EUV 16 Gb DDR5 DRAM Transistor Characteristics (opens in a new tab), TechInsights, Undated web article. Die measured at 7.40 mm by 7.11 mm (52.61 square millimetres) to the seal.
• Samsung D1z LPDDR5 DRAM with EUV Lithography (EUVL) (opens in a new tab), TechInsights (Jeongdong Choe), 16 April 2021. Samsung D1z 16 Gbit LPDDR5 die of 61.20 square millimetres; Micron D1z LPDDR4 comparison.
• Industry-leading DDR5 Technology: Micron vs. Samsung vs. SK hynix (opens in a new tab), TechInsights (Jeongdong Choe), Undated web article. Micron 16 Gbit DDR5 die of 66.26 square millimetres and bit density by vendor.
• Micron B47R 3D CTF CuA NAND Die, the World's First 176L (195T) (opens in a new tab), TechInsights, Undated web article, 2021. 512 Gbit TLC die of 49.84 square millimetres, 10.27 Gbit per square millimetre; 128-layer die for comparison.
• Micron 232-layer NAND now shipping (opens in a new tab), StorageReview (Lyle Smith), 26 July 2022. Micron's reported areal density of 14.6 Gbit per square millimetre for 232-layer TLC; the 1 Tbit die area follows from it.
• Intel 144-Tier Three-deck FG NAND with 161 Total Gates (opens in a new tab), Semiconductor Digest (analysis by Jeongdong Choe, TechInsights), 3 June 2021. Intel 144-layer 1 Tbit QLC die: 79.6 square millimetres, 12.86 Gbit per square millimetre.
• Samsung gives the 280-layer 3D NAND game away (opens in a new tab), Blocks and Files (Chris Mellor), 30 January 2024. Reported density of 28.5 Gbit per square millimetre for 280-layer QLC, used as an upper bound for the plausibility check.