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Register map builder

Define registers and their fields once, check addresses, widths and overlaps, and produce the documentation table and the C header that software uses.

Digital and physical designFor membersHow it worksSourcesWhere it helps

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How it works

A register map is the contract between the hardware and the software that drives it. Write each register and field once here, check the addresses, widths and overlaps, then take the C header, the documentation table and a SystemRDL description from the same rows, so they never disagree.

  1. Describe the block. Give the base address, the register width (8, 16, 32 or 64 bits), whether offsets are counted in bytes or in register-wide words, the byte order and the C prefix. A word offset is multiplied by the register width in bytes to give the byte offset used everywhere else.byte offset = offset x (width / 8) when offsets are in words, otherwise offset
  2. List the fields. One row per field: the register name, its offset in hexadecimal, the field name, its high and low bit, the access type, the reset value and a description. Rows with the same register name form one register. Leave the low bit empty for a single-bit field. Reset values take 0x for hexadecimal, 0b for binary or a Verilog style value such as 4'b0101; plain digits are read as hexadecimal.
  3. Run the checks. Each register offset must be a multiple of the register width in bytes. Registers must not overlap in address; fields must not overlap in bits and must lie inside the width; a reset value must fit its field; names must be unique and must not become the same C name. Gaps between registers and reserved bits are listed as notes, because software should treat them as reserved.register r covers [offset, offset + width / 8); fields a and b overlap when mask(a) AND mask(b) is not zero
  4. Assemble the reset value. The reset value of a register is each field's reset value shifted to its low bit and added together. Bits no field covers reset to zero.reset(register) = sum over fields of (reset(field) << low bit)
  5. Generate the outputs. The C header has the base address, then for each register its offset, address, reset value and a volatile access macro, and for each field its shift, mask, a GET macro and a VAL macro. It can add a structure of the whole block with padding for the gaps and a size check, and a bit-field union per register. The documentation table lists register, offset, field, bits, access, reset and description, and downloads as CSV. The SystemRDL text declares an address map with registers at their offsets and fields with software and hardware access properties.mask = ((1 << (high − low + 1)) − 1) << low; field = (value AND mask) >> low

Assumptions

  • Every register in the block has the same width, and registers are placed on multiples of that width.
  • A field with no reset value resets to zero.
  • The access types are the common software views: RW, RO, WO, W1C (write one to clear), W1S (write one to set), RC (clear on read) and RS (set on read). Hardware behaviour beyond that is described in the field's text.
  • The volatile flag marks fields hardware can change. The C register macros and the structure are always volatile, as for any memory-mapped register; the flag shows in the comments and the table and sets the hardware access in the SystemRDL output.
  • The bit-field order is that of GCC and Clang for the chosen byte order. The C standard leaves the order to the compiler.

Limits and warnings

  • Not an IP-XACT or CMSIS-SVD exporter. Those are XML formats with many more elements (memory maps, address blocks, enumerated values, interrupts, clocks); this tool does not write them.
  • The SystemRDL text covers registers, fields, access, reset and description only. Arrays, register files, aliases, enumerations, interrupt and counter properties are not written. Compile the result with a SystemRDL compiler before relying on it.
  • Read and write side effects other than the listed access types, write-once fields and fields with different read and write meanings need extra rows or a note in the description.
  • Offsets above 2^53 bytes are refused. Memory regions and arrays of registers are not modelled.

Sources

The methods and default figures rest on these public sources. The wording here is our own; read the source for its full text.

Where it helps

The lifecycle stages this tool serves: 7 stages in 4 lifecycles.

Terms on this page

Register map
The documented list of a device's programmable registers with addresses, bit fields, reset values and access rights.
Verilog
A hardware description language using a C-like syntax, standardised as IEEE 1364, used to describe designs at behavioural, RTL and gate level and to write simple simulation testbenches.
Memory map
The assignment of address ranges in a processor's address space to memories, peripherals and bus targets, defining what software sees at each address and how the interconnect decodes transactions.
RC delay
The signal delay of a wire set by its resistance multiplied by its capacitance.
GCC
The long-established free software compiler suite supporting C, C++, Ada, Fortran and more, with back ends for nearly every embedded architecture.
IP-XACT
An IEEE-standard XML schema for describing IP blocks, their interfaces, register maps, parameters and system connectivity in a tool-neutral way.
SVD
A CMSIS XML format describing a device's peripherals, registers and bit fields, from which vendors generate header files and debuggers build register views.

The full glossary

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