FPGA resource and device sizing estimator
Estimate logic, memory, DSP, transceiver and IO needs from your blocks, add margin, and see which device sizes fit and how full each would be.
Digital and physical designFree to useHow it worksSourcesWhere it helps
Fills the inputs below with typical figures. Replace any of them with your own.
- Smallest device that fits
- AMD Artix-7 XC7A200T
- Logic (LUT6 equivalents) limits it, at 48.1% of a 75% ceiling
- Logic needed
- 64,680
- LUT6 equivalents with margin; 81,180 flip-flops
- Memory needed
- 3,327 kbit
- block RAM, with margin
- DSP slices
- 101
- with margin
- Transceivers
- 4
- 4 at 3.4 Gb/s
- Pins
- 108
- 31 wide-range, 77 fast, with spare
Each bar is demand over the device's capacity. Ceilings: 75% for logic, memory and DSP; 100% for transceivers, pins and clocks.
- Logic (LUT6 equivalents)48.1%ceiling 75%
- Flip-flops30.2%ceiling 75%
- Block RAM25.3%ceiling 75%
- DSP slices13.6%ceiling 75%
- Transceivers25.0%ceiling 100%
- Pins needing up to 3.3 V6.2%ceiling 100%
- All user I/O pins21.6%ceiling 100%
- Clock managers (PLL or MMCM tiles)60.0%ceiling 100%
Show the data as a table
| Item | Utilisation |
|---|---|
| Logic (LUT6 equivalents) | 48.1% |
| Flip-flops | 30.2% |
| Block RAM | 25.3% |
| DSP slices | 13.6% |
| Transceivers | 25.0% |
| Pins needing up to 3.3 V | 6.2% |
| All user I/O pins | 21.6% |
| Clock managers (PLL or MMCM tiles) | 60.0% |
| Vendor | Smallest that fits | Limiting resource | Its utilisation |
|---|---|---|---|
| AMD | AMD Artix-7 XC7A200T | Logic (LUT6 equivalents) | 48.1% |
| Altera | Altera Agilex 7 F-Series AGF 006 | Logic (LUT6 equivalents) | 33.3% |
| Lattice | None fits | none | no result |
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| Device | Fits | Limiting resource | Logic | Flip-flops | Block RAM | Large RAM | DSP | Transceivers | I/O pins | Clocks |
|---|---|---|---|---|---|---|---|---|---|---|
| Lattice ECP5 LFE5U-25 | No | Transceivers | 539.0% | 338.3% | 330.1% | 0.0% | 360.7% | none on device | 54.8% | not checked |
| AMD Artix-7 XC7A35T | No | Logic (LUT6 equivalents) | 311.0% | 195.1% | 184.8% | 0.0% | 112.2% | 100.0% | 43.2% | 120.0% |
| Altera Cyclone 10 GX 10CX085 | No | Logic (LUT6 equivalents) | 208.6% | 65.5% | 57.2% | 0.0% | 120.2% | 66.7% | 50.0% | 100.0% |
| Lattice ECP5-5G LFE5UM5G-85 | No | Logic (LUT6 equivalents) | 154.0% | 96.6% | 88.9% | 0.0% | 64.7% | 100.0% | 29.6% | not checked |
| AMD Artix UltraScale+ AU15P | No | Clock managers (PLL or MMCM tiles) | 83.2% | 52.2% | 64.2% | 0.0% | 17.5% | 33.3% | 47.4% | 200.0% |
| Altera Cyclone 10 GX 10CX220 | No | Logic (LUT6 equivalents) | 80.5% | 25.3% | 28.3% | 0.0% | 52.6% | 33.3% | 38.0% | 60.0% |
| Lattice Avant-E LAV-AT-E30 | No | Transceivers | 79.4% | 49.8% | 23.1% | 0.0% | 14.4% | none on device | 30.9% | 85.7% |
| AMD Artix-7 XC7A200T | Yes | Logic (LUT6 equivalents) | 48.1% | 30.2% | 25.3% | 0.0% | 13.6% | 25.0% | 21.6% | 60.0% |
| Altera Agilex 7 F-Series AGF 006 | Yes | Logic (LUT6 equivalents) | 33.3% | 10.4% | 5.8% | 0.0% | 6.2% | 12.5% | 18.8% | not checked |
| Lattice Avant-E LAV-AT-E70 | No | Transceivers | 32.6% | 20.4% | 9.3% | 0.0% | 5.6% | none on device | 19.5% | 54.5% |
| AMD Kintex UltraScale+ KU5P | No | Clock managers (PLL or MMCM tiles) | 29.8% | 18.7% | 19.3% | -0.0% | 5.5% | 25.0% | 35.5% | 150.0% |
| Altera Agilex 7 F-Series AGF 014 | Yes | Logic (LUT6 equivalents) | 13.3% | 4.2% | 2.3% | 0.0% | 2.2% | 8.3% | 14.1% | not checked |
| AMD Kintex UltraScale+ KU15P | Yes | Clock managers (PLL or MMCM tiles) | 12.4% | 7.8% | 9.4% | -0.0% | 5.1% | 5.3% | 16.2% | 54.5% |
| Altera Agilex 7 F-Series AGF 027 | Yes | All user I/O pins | 7.1% | 2.2% | 1.3% | 0.0% | 1.2% | 4.5% | 14.5% | not checked |
| AMD Virtex UltraScale+ VU9P | Yes | Clock managers (PLL or MMCM tiles) | 5.5% | 3.4% | 4.3% | -0.0% | 1.5% | 3.3% | 10.5% | 20.0% |
| Device | Source and assumptions |
|---|---|
| AMD Artix-7 XC7A35T | DS180 v2.6.1: 5,200 slices of 4 LUTs and 8 flip-flops; 50 block RAMs; 5 clock management tiles; 4 GTP transceivers; 250 user I/O, all high-range. Transceivers are not bonded in every package. |
| AMD Artix-7 XC7A200T | DS180 v2.6.1: 33,650 slices; 365 block RAMs; 10 clock management tiles; 16 GTP transceivers; 500 user I/O, all high-range. |
| AMD Artix UltraScale+ AU15P | DS890 v4.10: 144 block RAMs, no UltraRAM, 3 clock management tiles, 12 transceivers, 156 high-performance and 72 high-density I/O. Line rate is 12.5 Gb/s in most packages and 16.3 Gb/s in FFVB676. AMD data sheet, one block RAM is 36 kbit and one UltraRAM block is 288 kbit. I/O is the largest count over all packages; a package has fewer. Transceiver rate can be package limited. |
| AMD Kintex UltraScale+ KU5P | DS890 v4.10: 480 block RAMs, 64 UltraRAM blocks, 4 clock management tiles, 16 GTY transceivers, 208 high-performance and 96 high-density I/O. Line rate is package limited. AMD data sheet, one block RAM is 36 kbit and one UltraRAM block is 288 kbit. I/O is the largest count over all packages; a package has fewer. Transceiver rate can be package limited. |
| AMD Kintex UltraScale+ KU15P | DS890 v4.10: 984 block RAMs, 128 UltraRAM blocks, 11 clock management tiles, 44 GTH and 32 GTY transceivers, 572 high-performance and 96 high-density I/O. AMD data sheet, one block RAM is 36 kbit and one UltraRAM block is 288 kbit. I/O is the largest count over all packages; a package has fewer. Transceiver rate can be package limited. |
| AMD Virtex UltraScale+ VU9P | DS890 v4.10: 2,160 block RAMs, 960 UltraRAM blocks, 30 clock management tiles, 120 GTY transceivers, 832 high-performance I/O and no high-density I/O. AMD data sheet, one block RAM is 36 kbit and one UltraRAM block is 288 kbit. I/O is the largest count over all packages; a package has fewer. Transceiver rate can be package limited. |
| Altera Cyclone 10 GX 10CX085 | Cyclone 10 GX Device Overview: 31,000 ALMs, 124,000 registers, 5,820 kbit M20K, 84 variable-precision DSP blocks, 6 transceivers, 216 GPIO, 2 fractional and 4 I/O PLLs. Logic is counted in ALMs. All GPIO is entered as one pool; check which banks support your voltage. |
| Altera Cyclone 10 GX 10CX220 | Cyclone 10 GX Device Overview: 80,330 ALMs, 321,320 registers, 11,740 kbit M20K, 192 variable-precision DSP blocks, 12 transceivers, 284 GPIO, 4 fractional and 6 I/O PLLs. Logic is counted in ALMs. |
| Altera Agilex 7 F-Series AGF 006 | Agilex 7 Device Overview, maximum values: 194,400 ALMs, 2,844 M20K blocks, 1,640 variable-precision DSP blocks, 32 F-tile channels at 32 Gb/s NRZ, 576 GPIO in the 2340A package. Registers are taken as 4 per ALM, the ratio of the Cyclone 10 GX table. PLL counts are not entered, so clocks are not checked. |
| Altera Agilex 7 F-Series AGF 014 | Agilex 7 Device Overview, maximum values: 487,200 ALMs, 7,110 M20K blocks, 4,510 variable-precision DSP blocks, 32 F-tile channels at 32 Gb/s and 16 E-tile channels at 28.9 Gb/s NRZ, 768 GPIO in the 2486A package. Registers are taken as 4 per ALM. PLL counts are not entered. |
| Altera Agilex 7 F-Series AGF 027 | Agilex 7 Device Overview, maximum values: 912,800 ALMs, 13,272 M20K blocks, 8,528 variable-precision DSP blocks, 64 F-tile channels at 32 Gb/s and 24 E-tile channels at 28.9 Gb/s NRZ, 744 GPIO in the 2340A package. Registers are taken as 4 per ALM. PLL counts are not entered. |
| Lattice ECP5 LFE5U-25 | ECP5 family table: 24K LUT4, 1,008 kbit EBR, 28 18x18 multipliers, no SERDES, 197 I/O. Lattice lists no flip-flop count here, so one per LUT4 is assumed. One LUT4 is taken as half a LUT6 for the estimate. PLL counts are not entered. |
| Lattice ECP5-5G LFE5UM5G-85 | ECP5 family table: 84K LUT4, 3,744 kbit EBR, 156 18x18 multipliers, 4 SERDES channels (5G family), 365 I/O in the largest package. One flip-flop per LUT4 and half a LUT6 per LUT4 are assumptions. |
| Lattice Avant-E LAV-AT-E30 | Avant-E selection table: 163K LUTs, 400 EBR blocks of 36 kbit, 700 18x18 multipliers, 7 PLLs, 349 user I/O in CBG484. The table gives no flip-flop count and no SERDES count, so one flip-flop per LUT and no transceivers are entered; check the Avant data sheet. Half a LUT6 per Lattice LUT is an assumption. |
| Lattice Avant-E LAV-AT-E70 | Avant-E selection table: 397K LUTs, 990 EBR blocks of 36 kbit, 1,800 18x18 multipliers, 11 PLLs, 553 user I/O in the largest packages. No flip-flop or SERDES counts are given, so one flip-flop per LUT and no transceivers are entered. Half a LUT6 per Lattice LUT is an assumption. |
How it works
Before choosing an FPGA, a team needs to know how much logic, memory, DSP, transceiver and I/O capacity the design will use, and how full a device can be before timing and routing get hard. This tool adds up the design blocks, applies growth and estimate margins, and checks the result against an editable table of real devices to find the smallest one that fits under your utilisation ceiling.
- Add up the blocks. Each block lists the resources one copy uses, from a synthesis report or an IP data sheet, and how many copies there are. Differential pairs count as two pins. Transceivers are kept by line rate, because a fast lane cannot run on a slow transceiver.
total resource = sum over blocks of (copies x resource per copy); fast pins = single-ended fast pins + 2 x pairs - Add the margins. Logic, flip-flops, memory and DSP slices carry a growth margin for future features and an estimate margin for the error in early numbers. Spare pins are kept on I/O, and clocks carry the growth margin. Transceivers carry none, because their count is a fixed design decision.
demand = ceiling(total x (1 + growth) x (1 + estimate margin)); pins = ceiling(total x (1 + spare)); clocks = ceiling(total x (1 + growth)) - Put devices on one scale. Vendors count logic differently: AMD in 6-input LUTs, Altera in adaptive logic modules (ALMs), Lattice in 4-input LUTs. Each device row carries an equivalence factor to LUT6 equivalents. The factors are editorial estimates (1 for AMD LUTs and Altera ALMs, 0.5 for Lattice LUT4s) and should be replaced by the ratio you see for your own design.
device logic = LUTs listed x LUT6 equivalence factor - Hold each resource to its ceiling. A device is full long before every cell is used: routability and timing degrade as utilisation rises. The fabric ceiling (logic, flip-flops, memory and DSP) is typically set at 70 to 80%; AMD's methodology guide describes placement getting harder when several fabric resources average above about 75%. Transceivers, pins and clock tiles are fixed counts, so they can usually run closer to 100%.
utilisation = demand / device capacity; fits when utilisation <= ceiling for every resource - Move large RAM when a device has none. Large RAM (UltraRAM) exists only on some families. When the spill setting is on, any large RAM a device cannot hold under its ceiling is added to the block RAM demand for that device. The spill is a first-pass estimate; granularity and port widths differ between the two kinds of RAM.
large RAM placed = min(demand, device large RAM x ceiling); block RAM demand = block RAM + (large RAM demand − large RAM placed) - Match transceivers by rate. Each device has up to two groups of transceivers, each with a count and a maximum line rate. Demand is placed fastest first, each lane on the slowest group that can run at its rate and still has room. Any lane left over means the device does not fit.
fits when every lane finds a group with rate >= lane rate - Split the I/O. Pins that need 2.5 V or 3.3 V can only use wide-range pins. Pins at 1.8 V or lower, including differential and memory interfaces, can use either kind. The check is therefore two tests: wide-range demand against wide-range pins, and all demand against all pins.
wide demand <= wide pins; wide demand + fast demand <= wide pins + fast pins - Find the limit. Devices are ordered by logic capacity. The smallest that fits is the first with every resource under its ceiling. The limiting resource is the one closest to its ceiling, found by comparing each utilisation with its own ceiling.
ratio = utilisation / ceiling; limiting resource = the one with the largest ratio
Assumptions
- Device figures are the largest member of each device's table entry, in the vendors' units; a package has fewer pins and sometimes fewer or slower transceivers. Enter your package's counts for a real decision.
- Smallest means the least logic capacity, not the lowest price or power. Device cost, speed grade and availability are not modelled.
- Where a vendor table lists no flip-flop, transceiver or clock count (Lattice flip-flops and Avant-E transceivers, the Altera Agilex PLL counts, ECP5 PLLs), the row says what was assumed or left out. A clock count of zero means clocks are not checked for that device.
- The block sizes in the presets are editorial estimates for a typical case. Replace them with the numbers from your own synthesis reports or IP data sheets.
Limits and warnings
- An early estimate of logic is uncertain by tens of percent. Re-run the numbers after synthesis and again after place and route, using the post-optimisation utilisation report.
- Memory is counted in kbit with no allowance for width, depth or port shape, which can waste block RAM. Wide, shallow memories need more blocks than their bit count suggests.
- Timing difficulty depends on clock rate, fan-out, and how the design uses the fabric as well as on utilisation; a design at 60% can fail timing and one at 85% can pass.
- Hard blocks that are not listed here (PCIe controllers, Ethernet MACs, memory controllers, processors) are not checked. Add them as blocks only if they use fabric or pins, and check their availability in your package.
- Several devices on one board, die-to-die links and partial reconfiguration are outside this estimate.
Sources
The methods and default figures rest on these public sources. The wording here is our own; read the source for its full text.
- UltraScale Architecture and Product Data Sheet: Overview (DS890), v4.10 (opens in a new tab), AMD, 21 May 2026. Artix, Kintex and Virtex UltraScale+ device resources.
- 7 Series FPGAs Data Sheet: Overview (DS180), v2.6.1 (opens in a new tab), Xilinx (now AMD), 8 September 2020. Artix-7 device resources and the 4 LUT, 8 flip-flop slice.
- Cyclone 10 GX Device Overview (opens in a new tab), Altera (formerly Intel Programmable Solutions Group), 1 April 2019. Maximum resources of the 10CX085 and 10CX220.
- Agilex 7 FPGAs and SoCs Device Overview (document 683458), F-Series (opens in a new tab), Altera, current page, 23 October 2026. Core resources, transceivers and GPIO of AGF 006, 014 and 027.
- ECP5 and ECP5-5G Family Data Sheet (FPGA-DS-02012), version 3.4 (opens in a new tab), Lattice Semiconductor, 5 October 2025. ECP5 family comparison table.
- Avant-E product selection table, with the Avant Platform Specifications Data Sheet (FPGA-DS-02112) (opens in a new tab), Lattice Semiconductor, product page read 25 October 2026; data sheet version 1.3, 19 May 2026. LAV-AT-E30 and E70 logic, memory, DSP, PLL and I/O.
- UltraFast Design Methodology Guide for FPGAs and SoCs (UG949), section Lower Device Utilization, 2026.1 (opens in a new tab), AMD, 23 June 2026. Review each resource separately; placement gets harder when several resources average above 75%.
- AN 903: Accelerating Timing Closure in Quartus Prime Pro Edition, section Reduce Congestion for High Utilization (opens in a new tab), Altera, 25 February 2021. Why very full devices lower fmax and how to reduce congestion.
Where it helps
The lifecycle stages this tool serves: 5 stages in 4 lifecycles.
More digital and physical design tools
Method notev1Formula, ranges, sources and limits
Adds up the logic, flip-flops, memory, DSP slices, transceivers, I/O and clocks of a design's blocks, applies growth and estimate margins, and finds the smallest device in an editable table that fits under a utilisation ceiling, with the limiting resource.
Formula
total resource = sum over blocks of (copies x resource per copy); fast pins = single-ended fast pins + 2 x pairs; demand = ceiling(total x (1 + growth) x (1 + estimate margin)); pins = ceiling(total x (1 + spare)); clocks = ceiling(total x (1 + growth)); device logic = LUTs listed x LUT6 equivalence factor; utilisation = demand / device capacity; fits when utilisation <= ceiling for every resource; large RAM placed = min(demand, device large RAM x ceiling); block RAM demand = block RAM + (large RAM demand − large RAM placed); fits when every lane finds a group with rate >= lane rate; wide demand <= wide pins; wide demand + fast demand <= wide pins + fast pins; ratio = utilisation / ceiling; limiting resource = the one with the largest ratio
| Input | Unit | Range it holds for | Comes from |
|---|---|---|---|
| Growth margin for future features | % | 0 to 200 | Your figure |
| Estimate margin | % | 0 to 200 | Your figure |
| Utilisation ceiling for logic, memory and DSP | % | 30 to 100 | Your figure |
| Ceiling for transceivers, pins and clocks | % | 30 to 100 | Your figure |
| Spare pins | % | 0 to 100 | Your figure |
| Vendor filter | choice | all, amd, altera, lattice | Your figure |
| Move large RAM to block RAM when a device has none | choice | yes, no | Your figure |
Outputs: Logic needed with margin (LUT6 equivalents); Block RAM needed with margin (kbit); DSP slices needed with margin (slices); Logic capacity of the smallest device that fits (LUT6 equivalents); Utilisation of the limiting resource on that device (%).
Assumptions
- Device figures are the largest member of each device's table entry, in the vendors' units; a package has fewer pins and sometimes fewer or slower transceivers. Enter your package's counts for a real decision.
- Smallest means the least logic capacity, not the lowest price or power. Device cost, speed grade and availability are not modelled.
- Where a vendor table lists no flip-flop, transceiver or clock count (Lattice flip-flops and Avant-E transceivers, the Altera Agilex PLL counts, ECP5 PLLs), the row says what was assumed or left out. A clock count of zero means clocks are not checked for that device.
- The block sizes in the presets are editorial estimates for a typical case. Replace them with the numbers from your own synthesis reports or IP data sheets.
Uncertainty: The arithmetic is exact. The result is as good as the block estimates and the device figures: early estimates differ from post-route numbers by tens of percent, and the LUT6 equivalence factors for ALMs and LUT4s are editorial.
Known limits
- An early estimate of logic is uncertain by tens of percent. Re-run the numbers after synthesis and again after place and route, using the post-optimisation utilisation report.
- Memory is counted in kbit with no allowance for width, depth or port shape, which can waste block RAM. Wide, shallow memories need more blocks than their bit count suggests.
- Timing difficulty depends on clock rate, fan-out, and how the design uses the fabric as well as on utilisation; a design at 60% can fail timing and one at 85% can pass.
- Hard blocks that are not listed here (PCIe controllers, Ethernet MACs, memory controllers, processors) are not checked. Add them as blocks only if they use fabric or pins, and check their availability in your package.
- Several devices on one board, die-to-die links and partial reconfiguration are outside this estimate.
Where the method comes from
The Hub's own resource roll-up. The utilisation guidance follows the vendors' methodology guides named in the sources; the device table is copied from their public data sheets and is editable.
Reference example, checked by test: Worked example in this method note: the 1080p60 video pipeline preset (49,000 LUTs, 61,500 flip-flops, 2,520 kbit block RAM, 76 DSP slices, 4 transceivers at 3.4 Gb/s, 5 clock tiles), 20% growth, 10% estimate margin, 75% ceiling, hand-worked in the tool's unit test against the device table. Logic needed with margin 64,680; Block RAM needed with margin 3,327; DSP slices needed with margin 101; Logic capacity of the smallest device that fits 134,600; Utilisation of the limiting resource on that device 48.0535.
Versions
- v1 (2026-10-25): First version, built from the tool idea.
Terms on this page
- DSP
- A processor architected for streaming numerical signal work, with multiply-accumulate hardware, saturating arithmetic, circular buffers and deterministic timing.
- Transceiver
- An integrated device combining the transmit and receive signal chains for a communication link, typically including LNA, mixers, filters, VGAs, synthesiser and data converters.
- I/O
- Input/output (I/O): the signals, pins and circuits through which a chip exchanges data with the outside world, together with their electrical standards.
- FPGA
- A chip containing an array of configurable logic blocks, programmable interconnect and embedded memory and DSP resources, whose function is defined after manufacture by loading a configuration bits...
- Utilisation
- The fraction of available placeable core area consumed by cell and macro instances, typically quoted as a percentage.
- Logic synthesis
- The translation of RTL into a gate-level netlist built from a specific standard cell library, subject to timing, area and power constraints.
- IP
- Intellectual property (IP).
- Datasheet
- The authoritative customer-facing document giving a part's electrical characteristics, absolute maximum ratings, timing, pinout, package drawing and ordering information.
- Flip-flop
- An edge-triggered storage element that captures its data input at a clock edge and holds it until the next edge, forming the basic register bit of synchronous digital design.
- Look-up table
- A small memory in an FPGA logic block that implements any logic function of its inputs by storing the output for every input combination.
- Speed grade
- A performance class in which a programmable device or other part is sold, set from characterisation and sorted by binning tests.
- PLL
- A feedback system that drives an oscillator so that its output phase tracks a reference, typically with a frequency divider in the loop to multiply the reference up.
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