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Qualification test planner

Build a reliability qualification plan for your product grade and package: which stress tests apply, lots, sample sizes, conditions, durations, devices and schedule.

ReliabilityFor membersHow it worksSourcesWhere it helps

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How it works

A qualification plan says which stress tests a product must pass before it ships, on how many lots and parts, under which conditions and for how long. This planner proposes the tests for your product's grade, package and features, lets you edit every row, and totals the parts, the lab weeks, the schedule and the cost.

  1. Choose the product category. Automotive parts follow the AEC-Q100 method and its temperature grades; commercial and industrial parts follow the JESD47 method. The grade sets the stress temperatures, for example the HTOL ambient and the temperature cycling range.
  2. Describe the package and features. The package decides the package integrity tests (wire bond shear and pull, solder ball shear, solderability) and whether moisture preconditioning comes first. Embedded non-volatile memory adds endurance and retention; a part that dissipates 1 W or more adds power temperature cycling.
  3. Use family data where it applies. A derivative, a package change or a die shrink can rely on data from a qualified family. The planner drops the die stresses for a package-only change and the package stresses for a die-only change, and marks where family data may reduce the lots; the justification is yours to record.
  4. Count the parts. Each row needs lots times parts per lot. The main stresses use three lots of 77 parts with zero failures: 231 parts without a failure show, at 90% confidence, that fewer than 1% of parts would fail that stress.parts = sum over tests of (lots x parts per lot)
  5. Build the schedule. Each test takes its stress time in weeks (168 hours a week, cycling at about two cycles an hour) plus a week for set-up and readouts. A test that follows another starts when that one ends; the rest start when the test boards are ready. The schedule is the longest chain.weeks = ceiling(stress hours / 168) + 1; schedule = board weeks + longest chain of weeks
  6. Track it. Each row carries a status (planned, running, passed, failed). A failure needs failure analysis and corrective action before the plan goes on.

Assumptions

  • The proposed conditions are a Hub template written from the published methods as commonly applied; check every row against the revision of the standard you qualify to.
  • Zero failures are allowed on every stress unless you change the row.
  • Stresses after preconditioning start when preconditioning ends; tests without a predecessor run in parallel once the boards are ready.
  • Costs come from your own figures: a cost per row, or a cost per device hour for the timed stresses.

Limits and warnings

  • Not the standard itself: tables, options and exceptions in AEC-Q100 and JESD47 are not reproduced here.
  • Product-specific tests (EMC, soft error rate, short circuit, gate leakage, defect screening) are left for you to add as rows.
  • Lab capacity and chamber sharing are not modelled; the schedule assumes chambers are free.
  • Family qualification rules vary by customer; agree the reuse with the customer before relying on it.

Sources

The methods and default figures rest on these public sources. The wording here is our own; read the source for its full text.

Where it helps

The lifecycle stages this tool serves: 24 stages in 20 lifecycles.

Terms on this page

Product qualification
The planned set of stress tests and evaluations showing that a part, built on its production process and package, will be reliable in its intended use.
AEC-Q100
The qualification specification that defines the stress tests, temperature grades and sample requirements an integrated circuit must pass to be sold as automotive grade.
JESD47
The JEDEC standard that defines the set of stress tests, sample sizes and acceptance criteria required to qualify a commercial integrated circuit for production.
HTOL
The core reliability stress in which parts run with dynamic stimulus at elevated temperature and often elevated voltage, usually 1000 hours at 125 °C, to accelerate intrinsic wear-out and generate...
Temperature cycling
Repeated cycling of a device between hot and cold extremes in air, for example minus 55 to 125 °C, to accelerate fatigue at interfaces caused by thermal expansion mismatch.
Wire bonding
Connecting die bond pads to package leads or substrate fingers with fine gold, copper or aluminium wire, formed loop by loop using heat, ultrasonic energy and force.
Solder ball
The spherical solder interconnect attached to the underside of a BGA or CSP that forms the second level joint to the printed circuit board.
Endurance
How much data a storage device can absorb before its flash wears out, expressed as drive writes per day or total bytes written over the warranty term.
Power cycling
A reliability test in which a module is repeatedly self-heated by load current and cooled, producing large junction temperature swings.
Die
A single rectangular block of processed silicon cut from a finished wafer, carrying one complete circuit.
Lot
The unit of material movement in a fab: a group of wafers, conventionally up to 25, that travel together through the process flow and share a lot number, run card and dispatch priority.
Failure analysis
The disciplined investigation of a failed device, moving from non-destructive checks and electrical characterisation through fault localisation to physical inspection, in order to identify the fail...

The full glossary

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