Die area estimator

How it works

Early in a project the die size sets the cost, the package and the schedule, and it has to be guessed from block counts. This tool adds up logic, SRAM, hard IP and analog areas from published density figures, adds routing space, the I/O ring and the seal ring, then checks whether the pads or bumps need more silicon than the circuits do.

1. Size the logic. Logic is counted in gate equivalents (one two-input NAND is four transistors). Divide by the node's peak density to get the area at perfect packing, then by the placement utilisation, which is the share of the placement area covered by cells.logic area = gates x transistors per gate / logic density / placement utilisation
2. Size the SRAM. A bit costs the area of its bitcell. The cell is only part of a macro: sense amplifiers, decoders and redundancy take the rest. Array efficiency is the cell share of the macro.SRAM area = Mbit x 1,048,576 x bitcell area / array efficiency / 1,000,000
3. Add hard IP and analog. Hard IP blocks (interface PHYs, PLLs, memories from a compiler) come as areas from their datasheets. Analog and mixed-signal area is entered as a total.IP area = sum of (block area x count)
4. Add routing and whitespace. Top-level channels, the power grid, block spacing and an imperfect floorplan add area on top of the blocks.core area = (logic + SRAM + IP + analog [+ I/O cells for flip chip]) x (1 + overhead)
5. Wrap the core in the ring and seal ring. For a wire-bonded die the I/O ring runs round the core and the seal ring round that. The core has the aspect ratio you choose (width over height).core width = sqrt(core area x aspect); core height = sqrt(core area / aspect); core-limited die = (core width + 2 x (ring depth + seal)) x (core height + 2 x (ring depth + seal))
6. Check the pads or bumps. Wire-bond pads sit round the edge, one per pad pitch, and rows of staggered pads multiply the count per length of edge. With k = sqrt(aspect) + 1 / sqrt(aspect), the die side u = sqrt(area) must give an edge long enough for every pad, less the corners. Flip chip puts bumps over the whole area on a grid.pad-limited die = ((I/O count x pad pitch / rows + 8 x (ring depth + seal)) / (2 x k))^2; bump-limited die = (sqrt(bumps x pitch^2 x aspect) + 2 x seal) x (sqrt(bumps x pitch^2 / aspect) + 2 x seal)
7. Take the larger and count the die on a wafer. The die size used is the larger of the core-limited, pad-limited and bump-limited sizes. The wafer count adds the scribe lane to each side of the die and uses the standard rectangular-die approximation shared with the die-per-wafer tool.die area = max(core-limited, pad-limited, bump-limited); gross die = floor(pi x (D/2)^2 / A − pi x D / sqrt(2 x A)), with D = wafer diameter − 2 x edge exclusion and A = (width + scribe) x (height + scribe)

Sources

The methods and default figures rest on these public sources. The wording here is our own; read the source for its full text.

• 10 nm technology leadership (opens in a new tab), Intel (Kaizad Mistry), Technology and Manufacturing Day, 28 March 2017. Logic transistor density by Intel node (45 nm to 10 nm) and the 10 nm high-density SRAM cell; a copy of the slides hosted by a university.
• The Truth of TSMC 5nm (opens in a new tab), Angstronomics (SkyJuice), 25 June 2022. Calculated transistor densities for 7 nm, 5 nm and 3 nm libraries from measured pitches, and why headline density figures differ.
• Intel, TSMC Tout SRAM Breakthroughs At 2nm (opens in a new tab), Mark LaPedus (Substack), 19 February 2025. High-density SRAM bitcell and macro density reported at ISSCC 2025 for TSMC N2 and Intel 18A.
• 7nm Processes at IEDM (opens in a new tab), Design And Reuse (coverage of IEDM, 3 to 7 December 2016), December 2016. TSMC's 7 nm SRAM cell of 0.027 square micrometres.