Writing synthesizable and verification-grade SystemVerilog per IEEE 1800: RTL that maps cleanly to the target library, interfaces and clocking blocks, classes and constrained-random stimulus, and the coding discipline that keeps simulation and synthesis semantics aligned.
No statement on what tools can do has been recorded for this skill yet.
Note from the research register: Taught by code review inside a design or DV team over the first two or three tapeouts, usually after a digital design course and a reading of the LRM plus a vendor coding guide.
Register version 1.