Low-Power Design Engineer

Project

Work done for a product or program.

• Define the power domain partitioning, voltage areas, always-on regions and power state table for the chip in collaboration with architects.
• Author and maintain the UPF (or CPF) power intent covering supply networks, power switches, isolation, level shifters, retention and repeaters.
• Run static low-power checks with VC LP or Conformal Low Power to prove structural correctness of the power intent at RTL and gate level.
• Run power-aware simulation with UPF applied to validate power-up, power-down, retention save/restore and isolation behaviour in every legal transition.
• Build power estimation flows from RTL activity, generating vectors from real use cases and producing early dynamic and leakage power budgets per block.
• Identify and drive RTL power reduction opportunities including clock gating efficiency, operand isolation, memory access reduction and data gating.
• Own the power budget tracking sheet per block and escalate overruns with quantified reduction proposals.
• Specify the power management unit sequencing contract with firmware, including handshake protocols, timers and acknowledge requirements.
• Correlate estimated power against silicon measurements and improve the estimation methodology accordingly.
• Review IP integration for power intent compliance and drive missing isolation or retention requirements back to IP owners.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Maintain design guidelines, coding standards and reusable blocks.General
• Improve design flows and checks with the CAD and methodology teams.General
• Mentor newer engineers and share lessons learned across projects.General

Project

1. Produce and hand over the role's key deliverables
   • Chip power architecture specification and power state table
   • UPF power intent files for RTL and netlist stages
   • Static low-power check and power-aware simulation signoff reports
   • Per-block dynamic and leakage power budget tracker
   • RTL power reduction proposals with quantified savings
   • PMU sequencing specification for firmware
2. Design the blockGeneral
   • Write or capture the design to the specification
   • Run lint, simulation or circuit checks
   • Close design reviews and their actions
3. Support integration and sign-offGeneral
   • Fix bugs found by verification
   • Support timing and physical closure
   • Deliver handoff files and documentation

Function

1. Keep design methods currentGeneral
   • Maintain coding and design standards
   • Build and maintain reusable blocks
2. Develop peopleGeneral
   • Mentor newer engineers
   • Run design reviews and knowledge sharing sessions