Also known as: Memory BIST Engineer; Memory Test Engineer (Embedded); Memory Repair Engineer
See this role on the Test program lifecycle or on the SoC lifecycle or on the Soft IP lifecycle
Makes every embedded SRAM, ROM, register file and eDRAM instance on an SoC self-testable, repairable and diagnosable, since embedded memories dominate both die area and defect density.
Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction
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