Roles / Design Verification Engineer

Design Verification Engineer

DV-001v1

Design VerificationVerificationIC2–IC6Individual contributor

Also known as: DV Engineer; Functional Verification Engineer; UVM Verification Engineer

See this role on the FPGA lifecycle or on the Automotive lifecycle or on the AI accelerator lifecycle or on the Startup lifecycle or on the Memory lifecycle or on the Space lifecycle or on the Medical lifecycle or on the Avionics lifecycle or on the Automotive SPICE lifecycle or on the FPGA chip lifecycle or on the Structured ASIC lifecycle or on the SoC lifecycle or on the Soft IP lifecycle

Summary

Proves through constrained-random simulation that an RTL design behaves exactly as specified before any silicon is committed, and finds the bugs that would otherwise become respins.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Lines tagged General are the Hub's general description of this kind of role, used where the role register has no entry yet. They are kept under review and will be refined.

Project

Work done for a product or program.

Write and maintain UVM testbenches including agents, drivers, monitors, sequencers, scoreboards and reference models for the assigned design block.
Translate the micro-architecture specification into a verification plan with enumerated features, stimulus requirements and coverage goals.
Develop constrained-random SystemVerilog sequences and directed tests that exercise corner cases, error injection and back-to-back protocol scenarios.
Build functional coverage models using covergroups and cross coverage, and drive coverage closure against the agreed verification plan.
Debug simulation failures in Verdi or Visualizer, isolate whether the root cause lies in RTL, testbench or specification, and file actionable bug reports in JIRA.
Run and triage nightly and weekly regressions, maintaining a green baseline and reporting failure signatures to the design team.
Write SystemVerilog assertions for interface protocols and internal design invariants to localise failures closer to their source.
Review RTL changes and design specification updates to assess verification impact and update the testbench accordingly.
Participate in verification plan reviews, testbench architecture reviews and tapeout signoff checklists with design and architecture teams.
Reproduce and verify silicon bug hypotheses raised by post-silicon validation teams in the pre-silicon simulation environment.

Function

Major tasks

Project

Produce and hand over the role's key deliverables
- Block-level UVM testbench and reusable verification environment
- Verification plan (vPlan) mapped to features and coverage points
- Constrained-random and directed test suite with regression lists
- Functional and code coverage reports with waiver justifications
- Block-level verification signoff report for tapeout review
Plan verificationGeneral
- Extract the features to verify from the specification
- Define coverage goals and the test strategy
- Review the plan with design and architecture
Close verificationGeneral
- Build testbenches and tests
- Run and triage regressions
- Report coverage and sign off

Function

Keep the methodology currentGeneral
- Maintain reusable verification components
- Update guidelines after each project
Improve the infrastructureGeneral
- Reduce regression run time
- Improve debug and coverage tools

Comp tier (within semis)

3 / 5

Remote feasibility

High

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Bangalore, Hyderabad, Noida, Austin, San Jose, Haifa, Shanghai, Hsinchu, Munich, Penang, Ho Chi Minh City

Certifications / standards training

Vendor UVM/SystemVerilog training (Synopsys, Cadence, Siemens EDA); Accellera UVM 1.2/IEEE 1800.2 methodology courses

Transfers to (industries)

FPGA-based aerospace and defence systems, automotive Tier-1 electronics, high-frequency trading hardware teams, safety-critical embedded software test

Risk if vacant

Blocks ship into SoC integration unverified, pushing bug discovery to full-chip or silicon where each escape costs a multi-million-dollar mask respin and a quarter of schedule.

Design Verification Engineer

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

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