RTL Design Engineer

Project

Work done for a product or program.

• Write synthesisable SystemVerilog RTL for assigned blocks from a micro-architecture specification, covering datapath, control FSMs and pipeline staging.
• Own the block micro-architecture document including pipeline diagrams, latency/throughput budgets, interface protocols and back-pressure schemes.
• Run trial synthesis in Design Compiler or Genus to close QoR early, fixing critical paths, high fan-out nets and congestion-prone structures before handing RTL to implementation.
• Clean lint, CDC, RDC and synthesis-pragma violations using SpyGlass or Meridian and justify every waiver with a documented rationale.
• Debug functional failures reported by the block and subsystem verification teams, triaging RTL bugs versus testbench or specification defects.
• Insert and validate clock gating, isolation, level shifters and retention flops consistent with the UPF power intent for the block.
• Implement DFT-friendly structures including scan-safe reset schemes, testable memories and clock-gate test-enable hookup agreed with the DFT team.
• Review peer RTL and micro-architecture specifications, enforcing coding guidelines and reuse of qualified design patterns.
• Support post-silicon bring-up by reproducing failures in simulation and proposing metal-fix or software workarounds where possible.
• Track and burn down block-level PPA, coverage and bug-rate metrics through each tapeout milestone.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.