Also known as: RTL Quality Signoff Engineer; Static Verification Engineer; Structural Checks Engineer
See this role on the FPGA lifecycle or on the AI accelerator lifecycle or on the Startup lifecycle or on the SoC lifecycle or on the Soft IP lifecycle
Runs and owns the static RTL quality gate — lint, CDC, RDC, X-propagation and structural DFT/power checks — so that structural defects never reach simulation, synthesis or silicon.
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