Emulation-to-Silicon Correlation Engineer

Project

Work done for a product or program.

• Port post-silicon test content to run unchanged on Palladium, Veloce and ZeBu emulation and on FPGA prototypes.
• Reproduce silicon failures in emulation with full internal visibility to identify the failing RTL condition.
• Quantify correlation gaps between emulation, gate-level simulation and silicon for performance, power and functional behaviour.
• Analyse which silicon bugs were reachable pre-silicon but missed and feed concrete coverage and stimulus gaps back to the DV team.
• Maintain a common test content architecture and hardware abstraction layer usable across simulation, emulation, FPGA and silicon.
• Correlate emulation-derived performance and bandwidth models against measured silicon workloads and refine the models.
• Drive the shift-left agenda by prioritising which post-silicon scenarios must be proven pre-silicon on the next project.
• Support hybrid debug sessions where silicon and emulation run the same stimulus for cycle-by-cycle comparison.
• Track and report bug escape metrics by category to inform verification strategy for the next programme.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Maintain the verification methodology, reusable components and coding guidelines.General
• Improve regression infrastructure, run time and debug tools with the CAD team.General
• Share failure analysis and escape reviews so later projects avoid the same bugs.General

Project

1. Produce and hand over the role's key deliverables
   • Portable test content running across simulation, emulation, FPGA and silicon
   • Bug escape analysis with pre-silicon coverage gap attribution
   • Emulation-to-silicon correlation reports for function, performance and power
   • Shift-left recommendations for the next verification plan
   • Emulation reproduction cases for open silicon bugs
2. Plan verificationGeneral
   • Extract the features to verify from the specification
   • Define coverage goals and the test strategy
   • Review the plan with design and architecture
3. Close verificationGeneral
   • Build testbenches and tests
   • Run and triage regressions
   • Report coverage and sign off

Function

1. Keep the methodology currentGeneral
   • Maintain reusable verification components
   • Update guidelines after each project
2. Improve the infrastructureGeneral
   • Reduce regression run time
   • Improve debug and coverage tools