Roles / DFT Implementation Engineer

DFT Implementation Engineer

TST-002v1

DFT & Test EngineeringTestIC2–IC6Individual contributor

Also known as: Scan Insertion Engineer; DFT RTL/Netlist Engineer; DFT Integration Engineer

See this role on the SoC lifecycle or on the Soft IP lifecycle or on the Automotive lifecycle or on the Test program lifecycle or on the Security lifecycle or on the Structured ASIC lifecycle or on the Hard IP lifecycle

Summary

Inserts and stitches the physical test structures — scan chains, test clock and reset control, wrappers and compression logic — into the design netlist so the architecture defined on paper actually exists in silicon.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Lines tagged General are the Hub's general description of this kind of role, used where the role register has no entry yet. They are kept under review and will be refined.

Project

Work done for a product or program.

Insert scan chains into gate-level netlists using Tessent or TestMAX, honouring clock domain, power domain and lockup latch rules.
Implement test clock and asynchronous reset control logic including OCC (on-chip clock controller) instantiation and bypass modes.
Run and clean DFT rule checks (DRC) in SpyGlass DFT or Tessent DesignForTest and drive scannability violations back to RTL owners.
Stitch IEEE 1500 wrappers around cores and integrate them into the chip-level IJTAG network.
Balance and reorder scan chains with the physical design team using placement-aware scan reordering to minimise routing congestion and wirelength.
Generate and hand off scan definition files, SPF/STIL protocol files and test mode setup collateral to the ATPG team.
Implement test mode decoding, test pin muxing and isolation logic for analog and mixed-signal blocks.
Verify inserted logic is functionally transparent in mission mode through equivalence checking and gate-level simulation.
Support ECO flows by re-inserting or patching scan connectivity after late netlist changes without breaking chain integrity.
Document the inserted DFT structures, chain counts, chain lengths and test modes in the release notes for each netlist drop.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Maintain test standards, test hardware and program libraries.General
Work with equipment and probe card suppliers on capacity and capability.General
Improve test methods and data tools for future products.General

Major tasks

Project

Produce and hand over the role's key deliverables
- Scan-inserted gate-level netlist with balanced chains
- Scan definition and STIL protocol files (SPF)
- DFT DRC clean report per test mode
- OCC and test control logic RTL / integration scripts
- Scan chain report with chain counts, lengths and clock domains
- Equivalence checking report between pre- and post-DFT netlists
Develop the test solutionGeneral
- Define the test plan and coverage targets
- Write and debug the test program
- Design or specify the test hardware
Release to productionGeneral
- Correlate results across testers and sites
- Optimise test time
- Release the program under change control

Function

Maintain test infrastructureGeneral
- Keep program libraries and standards current
- Plan tester and hardware capacity
Improve methodsGeneral
- Review escapes and adjust coverage
- Develop data analysis tools

Works with

Typical backgrounds

BS/MS in Electrical or Electronics Engineering; 2–10 years in DFT insertion, digital design or synthesis flows.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

3 / 5

Remote feasibility

High

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Bangalore / Hyderabad / Pune (India), Hsinchu, Shanghai, San Jose, Austin, Penang, Kraków

Certifications / standards training

Synopsys or Siemens EDA DFT tool certification; IEEE 1149.1/1500 training

Transfers to (industries)

Almost none outside chip design; adjacent only to FPGA prototyping and EDA tool support roles

Risk if vacant

Netlist drops stall because scan structures cannot be inserted or cleaned, blocking ATPG, timing signoff and tapeout schedules.

DFT Implementation Engineer

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

Register or sign in to read on