Memory Controller Design Engineer

Project

Work done for a product or program.

• Design the command scheduler that reorders reads and writes to maximise bank-level parallelism and row-buffer hit rate.
• Implement JEDEC timing parameter enforcement for tRCD, tRP, tFAW, tRRD, tWTR and refresh scheduling across DDR5, LPDDR5X, GDDR7 or HBM3E.
• Design ECC logic covering SECDED, on-die ECC interaction, link ECC, scrubbing and error reporting to system software.
• Implement low-power state machines for self-refresh, power-down and dynamic frequency and voltage scaling handoffs.
• Build QoS and arbitration between latency-sensitive and bandwidth-hungry masters such as CPU, GPU, camera and display.
• Analyse achieved efficiency on real traffic traces and tune scheduler policies to close bandwidth gaps.
• Support silicon bring-up on DDR training failures, marginality and vendor-specific DRAM behaviour.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Design the initialisation and training sequencer that coordinates write levelling, read training and periodic retraining with the PHY.
• Implement refresh management including per-bank refresh, temperature-controlled refresh and refresh postponement policies.
• Co-validate controller behaviour with the DFI interface to the PHY and with DRAM models across speed bins and vendors.

Project

1. Produce and hand over the role's key deliverables
   • Memory controller RTL including scheduler, timing engine and ECC
   • DFI-compliant PHY interface and training sequence implementation
   • Memory efficiency analysis across traffic profiles and speed bins
   • JEDEC compliance matrix and timing parameter configuration tables
   • Low-power state machine specification and validation results
   • Bring-up and debug guide for memory training
2. Design the blockGeneral
   • Write or capture the design to the specification
   • Run lint, simulation or circuit checks
   • Close design reviews and their actions
3. Support integration and sign-offGeneral
   • Fix bugs found by verification
   • Support timing and physical closure
   • Deliver handoff files and documentation

Function

1. Keep design methods currentGeneral
   • Maintain coding and design standards
   • Build and maintain reusable blocks
2. Develop peopleGeneral
   • Mentor newer engineers
   • Run design reviews and knowledge sharing sessions