FPGA Design Engineer

Project

Work done for a product or program.

• Design RTL targeted at a specific FPGA family, deliberately inferring or instantiating DSP slices, block RAM, URAM, LUT structures and hard IP blocks.
• Close FPGA timing through floorplanning with Pblocks, pipelining, physical optimisation and incremental implementation strategies.
• Integrate vendor IP and processing systems such as Zynq UltraScale+, Versal, Agilex or SmartFusion blocks with custom logic.
• Design and verify high-speed transceiver interfaces (GTY/GTH, E-tile) and external memory controllers on the target device.
• Manage resource utilisation budgets across LUTs, flip-flops, BRAM, DSP and transceivers with headroom for future features.
• Implement partial reconfiguration or multi-image configurations where the application requires field feature updates.
• Design for reliability in harsh or radiation environments using triple modular redundancy, ECC on block RAM and configuration memory scrubbing.
• Produce and maintain the FPGA build flow, constraint files and bitstream release process including version and revision control.
• Bring up designs on target hardware, debugging with integrated logic analysers and correlating against simulation.
• Support field updates, in-system reprogramming and long-term device obsolescence planning for shipping products.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Maintain design guidelines, coding standards and reusable blocks.General
• Improve design flows and checks with the CAD and methodology teams.General
• Mentor newer engineers and share lessons learned across projects.General

Project

1. Produce and hand over the role's key deliverables
   • Production FPGA RTL and vendor IP integration
   • Timing-closed implementation with constraint files (XDC/SDC)
   • Released bitstreams with build reproducibility records
   • Resource utilisation and timing closure reports
   • Hardware bring-up and debug documentation
   • Reliability mitigation design (TMR, scrubbing) where applicable
2. Design the blockGeneral
   • Write or capture the design to the specification
   • Run lint, simulation or circuit checks
   • Close design reviews and their actions
3. Support integration and sign-offGeneral
   • Fix bugs found by verification
   • Support timing and physical closure
   • Deliver handoff files and documentation

Function

1. Keep design methods currentGeneral
   • Maintain coding and design standards
   • Build and maintain reusable blocks
2. Develop peopleGeneral
   • Mentor newer engineers
   • Run design reviews and knowledge sharing sessions