DFX and Debug Logic Design Engineer

Project

Work done for a product or program.

• Architect the chip debug infrastructure including JTAG/IEEE 1149.1 and IEEE 1687 IJTAG networks, debug access ports and secure debug authentication.
• Design trace subsystems using Arm CoreSight components or equivalents, covering trace funnels, ETM/ETB buffers, timestamping and trace export over a parallel or high-speed port.
• Implement chip-level observability structures such as signal multiplexing to debug buses, event triggers, cross-triggering and programmable trigger matrices.
• Design performance monitoring units and error-logging registers that expose counters, stall reasons and error causes to software.
• Implement scan-dump, mem-dump and array-freeze mechanisms that capture internal state after a hang for post-mortem analysis.
• Design lockup and watchdog detection logic plus the reset and recovery escalation path for hung subsystems.
• Balance debug feature coverage against area, power and security risk, and gate debug capability behind lifecycle and authentication controls.
• Produce debug programming guides and bring-up scripts so that validation teams can use the hardware on day one of silicon.
• Support post-silicon debug sessions directly, interpreting trace and dump data and proposing additional observability for the next revision.
• Coordinate with the DFT team so that scan and debug infrastructure share resources without conflicting.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Maintain design guidelines, coding standards and reusable blocks.General
• Improve design flows and checks with the CAD and methodology teams.General
• Mentor newer engineers and share lessons learned across projects.General

Project

1. Produce and hand over the role's key deliverables
   • Debug and trace architecture specification
   • Debug infrastructure RTL including DAP, trace and trigger logic
   • Debug register map and programming guide
   • Bring-up and debug script collateral for validation teams
   • Secure debug authentication and lifecycle policy implementation
   • Post-silicon debug observability gap analysis for next revision
2. Design the blockGeneral
   • Write or capture the design to the specification
   • Run lint, simulation or circuit checks
   • Close design reviews and their actions
3. Support integration and sign-offGeneral
   • Fix bugs found by verification
   • Support timing and physical closure
   • Deliver handoff files and documentation

Function

1. Keep design methods currentGeneral
   • Maintain coding and design standards
   • Build and maintain reusable blocks
2. Develop peopleGeneral
   • Mentor newer engineers
   • Run design reviews and knowledge sharing sessions