Processor Verification Engineer

Project

Work done for a product or program.

• Build instruction-stream generators and configure random instruction generators such as riscv-dv, Google's RISCV-DV or in-house ISG frameworks to stress the pipeline.
• Run lockstep co-simulation of the RTL core against a golden instruction-set simulator such as Spike, Sail or an architectural reference model and compare state after every instruction.
• Verify exception, interrupt and trap behaviour including precise exception semantics, nested interrupts and privilege-level transitions.
• Verify memory ordering and consistency model compliance using litmus tests and memory model checkers for weakly-ordered architectures.
• Verify cache hierarchy and coherency behaviour including snooping, MESI/MOESI state transitions, atomics, exclusives and cache maintenance operations.
• Stress microarchitectural features such as branch prediction, out-of-order issue, load-store reordering, speculation recovery and pipeline flush paths.
• Verify MMU and virtual memory behaviour including page table walks, TLB coherency, permission faults and address translation edge cases.
• Verify debug, trace and performance monitoring unit behaviour against the architectural debug specification.
• Analyse and verify security-relevant speculative execution behaviour with respect to known side-channel attack classes.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Run architectural compliance suites such as the RISC-V Architecture Test Suite or Arm Architecture Validation Suite and close all failures.

Project

1. Produce and hand over the role's key deliverables
   • Instruction stream generator configurations and constraint libraries
   • ISS lockstep co-simulation environment with state comparison
   • Memory ordering and coherency test suite results
   • Architectural compliance suite results and waiver record
   • Microarchitectural coverage model for pipeline, branch prediction and speculation
   • Core verification signoff report
2. Plan verificationGeneral
   • Extract the features to verify from the specification
   • Define coverage goals and the test strategy
   • Review the plan with design and architecture
3. Close verificationGeneral
   • Build testbenches and tests
   • Run and triage regressions
   • Report coverage and sign off

Function

1. Keep the methodology currentGeneral
   • Maintain reusable verification components
   • Update guidelines after each project
2. Improve the infrastructureGeneral
   • Reduce regression run time
   • Improve debug and coverage tools