Clock and Reset Architecture Engineer

Project

Work done for a product or program.

• Define the chip clock tree architecture including PLL and DLL allocation, clock sources, reference distribution, dividers, muxes and spread-spectrum requirements.
• Design the clock generation and reset generation unit RTL, covering glitch-free clock switching, clock gating hierarchy and divider ratio programming.
• Specify the reset architecture including power-on reset, warm reset, functional reset domains, reset ordering and reset de-assertion synchronisation.
• Enumerate and document every clock domain crossing in the design and mandate the synchroniser scheme for each, then verify with CDC and RDC tools.
• Design dynamic frequency scaling and clock switching sequences that coordinate with power management firmware without dropping or glitching clocks.
• Own clock-related constraint generation, including generated clocks, clock groups and the async/exclusive relationships handed to STA.
• Coordinate with clock tree synthesis and physical design teams on skew budgets, useful skew, clock mesh versus tree decisions and jitter budgets.
• Review integration of every new IP for clock, reset and CDC compliance before it enters the chip hierarchy.
• Debug silicon issues involving clock start-up, reset ordering, lockups on frequency change and metastability-induced intermittent failures.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Specify asynchronous FIFO and handshake synchroniser cells and their meta-stability and MTBF assumptions for the library in use.

Project

1. Produce and hand over the role's key deliverables
   • Chip clock and reset architecture specification
   • CRG/RRG unit RTL and programming model
   • Clock domain crossing register and synchroniser policy document
   • Clock constraint and clock group definitions for STA
   • CDC and RDC signoff reports with reviewed waivers
   • DVFS and clock switching sequence specification
2. Design the blockGeneral
   • Write or capture the design to the specification
   • Run lint, simulation or circuit checks
   • Close design reviews and their actions
3. Support integration and sign-offGeneral
   • Fix bugs found by verification
   • Support timing and physical closure
   • Deliver handoff files and documentation

Function

1. Keep design methods currentGeneral
   • Maintain coding and design standards
   • Build and maintain reusable blocks
2. Develop peopleGeneral
   • Mentor newer engineers
   • Run design reviews and knowledge sharing sessions