Closing timing on a digital block or chip: writing and auditing SDC constraints, choosing corner and mode sets, handling clock groups, CPPR, OCV/AOCV/POCV derates and false or multicycle paths, and reading PrimeTime or Tempus reports well enough to tell a real violation from a constraint artifact.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: Learned over two or more tapeouts in a physical design or STA role under a signoff owner, after a basic digital timing course; the judgment comes from constraint reviews, not tools training.
Register version 1.