HBM Controller and PHY Digital Design Engineer

Project

Work done for a product or program.

• Implement HBM3 and HBM4 controller RTL with channel and pseudo-channel scheduling.
• Plan interposer-aware timing and lane-repair features with packaging teams.
• Tune address mapping and traffic arbitration for accelerator workloads.
• Integrate ECC, RAS and temperature-throttling features.
• Model bandwidth and power at the stack level.
• Support bring-up with memory vendors and system teams.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Design the PHY digital logic for wide parallel interfaces and training.

Project

1. Produce and hand over the role's key deliverables
   • HBM controller and PHY digital RTL
   • HBM subsystem specification
   • Bandwidth and power analysis
   • Vendor interoperability test reports
2. Support programsGeneral
   • Agree what each program needs
   • Deliver in time for milestones
3. Manage issuesGeneral
   • Track requests to closure
   • Escalate risks

Function

1. Run the functionGeneral
   • Maintain policies and processes
   • Keep records and controls
2. ImproveGeneral
   • Report performance
   • Lead improvement work