Also known as: Cryptographic Accelerator Design Engineer; Security IP RTL Engineer; Hardware Crypto Designer; Crypto Core Design Engineer
See this role on the FPGA chip lifecycle or on the SoC lifecycle or on the Soft IP lifecycle
Builds hardware crypto engines for encryption, hashing, signatures and post-quantum algorithms with side-channel resistance.
Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction
The role's tasks, work products, gates, skills, career paths, listings and pay benchmarks are for registered members. Registration is free and takes a minute. You come back to this page afterwards.