Memory Controller RTL Design Engineer

Project

Work done for a product or program.

• Implement command scheduling, bank management and refresh logic in RTL.
• Design ECC, scrubbing and error-reporting paths in the controller.
• Tune arbitration and QoS for bandwidth and latency targets.
• Integrate the controller with the PHY, interconnect and register interfaces.
• Meet DDR timing parameters across speed bins in design and constraints.
• Debug memory failures in emulation and silicon with training firmware teams.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Track JEDEC standard updates and evaluate new memory features.

Project

1. Produce and hand over the role's key deliverables
   • Memory controller RTL
   • Controller micro-architecture specification
   • Performance analysis against bandwidth targets
   • Integration and bring-up guide
2. Support programsGeneral
   • Agree what each program needs
   • Deliver in time for milestones
3. Manage issuesGeneral
   • Track requests to closure
   • Escalate risks

Function

1. Run the functionGeneral
   • Maintain policies and processes
   • Keep records and controls
2. ImproveGeneral
   • Report performance
   • Lead improvement work