Roles / EDA Algorithm Developer — Place & Route

EDA Algorithm Developer — Place & Route

EDA-002v1

EDA, CAD & Design InfrastructureResearchIC3–IC7Individual contributor

Also known as: Physical Design Algorithm Engineer; P&R Engine Developer; Placement/Routing R&D Engineer

See this role on the FPGA chip lifecycle

Summary

Invents and productises the optimisation algorithms inside placement, legalisation, clock tree synthesis and routing engines that determine achievable PPA at advanced nodes.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Project

Work done for a product or program.

Develop analytical and nonlinear global placement algorithms with density and timing-driven cost functions for multi-million-cell blocks.
Design detailed routing engines that honour advanced-node design rules including multi-patterning colouring, minimum area and via-pillar constraints.
Improve timing-driven optimisation loops so incremental resizing, buffering and useful-skew converge without QoR oscillation.
Formulate and solve combinatorial subproblems using integer linear programming, min-cost flow, SAT and graph partitioning techniques.
Benchmark engine QoR against competitor tools and previous releases on internal and customer designs, and quantify wirelength, congestion, timing and power deltas.
Scale algorithms across many cores and distributed machines while keeping run-to-run determinism for signoff reproducibility.
Prototype in Python or research code, then harden into production C++ with full regression coverage.
Publish and track state of the art at DAC, ICCAD, ISPD and the ISPD contests, and assess academic techniques for productisation.
Work with foundry enablement teams to support new design rules and technology files ahead of node ramp.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Mentor junior developers on CAD optimisation theory and QoR debugging methodology.

Major tasks

Project

Produce and hand over the role's key deliverables
- Production placement, CTS or routing engine improvements
- QoR benchmark reports versus baseline and competition
- Algorithm specifications and complexity analyses
- Patent disclosures and conference papers
- Node-enablement support for new DRC constructs
Run research projectsGeneral
- Define hypotheses and experiments
- Build test structures or models
- Analyse and report the results
Transfer resultsGeneral
- Hand findings over to development
- Support early adoption

Function

Stay currentGeneral
- Review the literature
- Work with universities and consortia
Protect and shareGeneral
- File invention disclosures
- Publish where allowed

Works with

EDA software engineers
timing engine developers
foundry enablement teams
lead physical design customers
product management

Typical backgrounds

MS/PhD in EE or CS with VLSI CAD or optimisation specialisation; 3–15 years in physical design algorithms

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

4 / 5

Remote feasibility

Medium

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Silicon Valley, Austin, Portland, Noida, Shanghai, Hsinchu, Grenoble, Munich

Certifications / standards training

—

Transfers to (industries)

Operations research and logistics optimisation, PCB and package design software, FPGA toolchains, graph analytics platforms

Risk if vacant

PPA competitiveness of the implementation product stalls and advanced-node design rules go unsupported, costing customer benchmark wins.

EDA Algorithm Developer — Place & Route

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

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