Process Technology glossary

Process technology terms describe how transistors and wiring are made on a wafer: process nodes, transistor structures such as planar, FinFET and gate-all-around, front-end and back-end steps, and the process design kit that tells designers what the process can do.

Process engineers, foundry customers and analysts use these terms to compare nodes, understand what a new transistor brings, and see how process choices affect cost, yield and design rules.

117 terms in 12 groups, 32 with a full explanation and examples. Each term has its own page.

Device physics

Carrier mobility: How readily electrons or holes move through the channel under an electric field, measured in cm2/V-s.
CMOS: Complementary Metal Oxide SemiconductorIn depth: A logic family that pairs n-channel and p-channel transistors so that one of them is always off in a static state, giving near-zero standby current.
DIBL: Drain-Induced Barrier Lowering: A short-channel effect in which a high drain voltage lowers the source-to-channel barrier, reducing threshold voltage and raising off-state leakage.
Drive current: The saturation current a transistor delivers when fully on, normalised per micron of device width or per device footprint.
EOT: Equivalent Oxide Thickness: The thickness of silicon dioxide that would give the same capacitance as the actual gate dielectric stack.
Gate oxideIn depth: The thin insulating layer separating the gate electrode from the channel, historically silicon dioxide and now a hafnium-based high-k stack.
GIDL: Gate-Induced Drain Leakage: Leakage generated in the gate-to-drain overlap region when a strong field there causes band-to-band tunnelling.
HKMG: High-k Metal Gate: A gate stack that replaces silicon dioxide with a high permittivity dielectric, usually hafnium based, and polysilicon with a metal electrode.
Leakage current: Current that flows when a transistor is nominally off, summing subthreshold conduction, gate tunnelling and junction leakage.
MOSFET: Metal Oxide Semiconductor Field Effect TransistorIn depth: The switching device that underpins nearly all digital logic, in which a voltage on an insulated gate creates or removes a conducting channel between source and drain.
Multi-Vt: Multiple threshold voltageIn depth: A process offering that provides several threshold-voltage variants of the same transistor, typically low, standard, high and ultra-high.
NMOS: N-channel Metal Oxide Semiconductor: A MOSFET whose channel conducts using electrons, built in a p-type body and turned on by a positive gate voltage.
PMOS: P-channel Metal Oxide Semiconductor: A MOSFET whose channel conducts using holes, built in an n-type well and turned on by a negative gate-to-source voltage.
SCE: Short-channel effect: The family of degradations that appear when the channel becomes short enough that the drain field, not just the gate, controls the channel.
Strain engineering: Deliberately straining the transistor channel to raise carrier mobility, using embedded silicon-germanium source/drain for compressive strain in PMOS and tensile nitride liners or silicon-carbon fo...
Subthreshold slope: The gate voltage change needed to move drain current by one decade below threshold, quoted in mV/decade.
Threshold voltageIn depth: The gate-to-source voltage at which a MOSFET channel begins to conduct meaningfully.
Work function metal: The metal layer in a high-k gate stack whose effective work function sets the device threshold voltage.

Foundry naming

22FDX: GlobalFoundries' 22 nm FD-SOI platform, offering back-bias, low leakage, integrated RF and non-volatile memory options.
A16: TSMC's 1.6 nm class node, named in angstroms rather than nanometres, combining nanosheet transistors with the Super Power Rail backside power delivery network.
FinFlex: TSMC's N3 feature that lets different standard cells in the same design use different fin configurations, such as two fins for density or three for performance.
Intel 18A: Intel's 1.8 nm class node, the first to combine its RibbonFET gate-all-around transistor with PowerVia backside power delivery.
N2: TSMC's 2 nm class process, its first using nanosheet gate-all-around transistors.
Process derivative: A tuned variant of an existing node that reuses most of the process and design rules while improving performance, power or density, marketed with a suffix such as P, E or plus.

Front-end process

ALD: Atomic Layer DepositionIn depth: Deposition using self-limiting surface reactions in alternating precursor pulses, adding roughly one atomic layer per cycle.
ALE: Atomic Layer Etching: Etching in self-limiting cycles that remove about one atomic layer at a time, using a surface modification step followed by a removal step.
AnnealingIn depth: A high-temperature step that repairs implant damage and moves dopants onto electrically active lattice sites.
Channel release: The selective removal of the sacrificial silicon-germanium layers from a Si/SiGe superlattice, leaving free-standing silicon channels for the gate to wrap.
CMP: Chemical Mechanical PlanarisationIn depth: Polishing the wafer flat using a rotating pad and an abrasive, chemically active slurry.
CVD: Chemical Vapour DepositionIn depth: Depositing a film by flowing precursor gases that react on the wafer surface.
DiffusionIn depth: The thermally driven spreading of dopant atoms through silicon.
Dry etchIn depth: Removing material with a plasma of reactive ions, which etches mostly downward and so reproduces the mask shape with near-vertical sidewalls.
EpitaxyIn depth: Growing a crystalline layer that continues the atomic lattice of the underlying substrate.
Ion implantationIn depth: Introducing dopants by accelerating ionised atoms into the wafer, with dose and energy setting concentration and depth.
LOCOS: Local Oxidation of Silicon: A legacy isolation method that grows thick field oxide in the areas between devices using a nitride mask.
PVD: Physical Vapour DepositionIn depth: Depositing a film by physically ejecting material from a target, usually by sputtering with an ion plasma, and letting it condense on the wafer.
RMG: Replacement Metal Gate: A gate-last integration flow in which a sacrificial polysilicon gate is formed, source and drain processing is completed, and the dummy gate is then removed and refilled with high-k and metal.
Silicide: A metal-silicon compound, usually nickel or titanium based, formed on source, drain and gate to cut contact resistance.
Spacer: A dielectric sidewall formed on the gate by depositing a conformal film and etching it back anisotropically.
STI: Shallow Trench Isolation: Electrical isolation between adjacent devices formed by etching a shallow trench, filling it with oxide and polishing it flat.
Thermal oxidationIn depth: Growing silicon dioxide by exposing silicon to oxygen or steam at high temperature, consuming silicon in the process.
Wafer cleaningIn depth: The repeated removal of particles, organics, metal contamination and native oxide between process steps.
Wet etch: Removing material with liquid chemistry, which is typically isotropic and highly selective between materials.

Interconnect and BEOL

Airgap: Deliberately leaving a void between adjacent metal lines so the dielectric constant approaches that of vacuum.
Barrier layer: A thin conductive film, typically tantalum nitride with a tantalum or cobalt liner, that keeps copper from diffusing into the surrounding dielectric and improves adhesion.
BEOL: Back End Of LineIn depth: The wiring half of wafer fabrication, building the stack of metal layers and dielectrics that interconnect the transistors.
Cobalt interconnect: Using cobalt instead of copper or tungsten in the tightest contacts and lowest metal layers, where copper's barrier overhead makes it lose its resistivity advantage.
Contact: The vertical connection from the transistor's source, drain or gate up to the first metal level.
Contact resistanceIn depth: The resistance at the metal-to-semiconductor junction of a contact, set mainly by the Schottky barrier height and the contact area.
Copper interconnect: Wiring made from electroplated copper rather than aluminium, giving lower resistivity and much better electromigration lifetime.
Damascene: An interconnect scheme in which trenches and vias are etched into dielectric, filled with metal, and the excess polished away.
ILD: Interlayer Dielectric: The insulating film separating successive metal levels and the transistors from the first metal.
InterconnectIn depth: The wiring that connects devices and blocks.
Low-k dielectric: An insulating material with permittivity below that of silicon dioxide, used between metal lines to reduce capacitance and RC delay.
Metal stackIn depth: The set of metal and via layers a process offers for wiring, with their number, thicknesses, pitches and materials.
RC delay: Resistance-capacitance delayIn depth: The signal delay of a wire set by its resistance multiplied by its capacitance.
Ruthenium interconnect: Ruthenium wiring for the tightest lines, attractive because it can run barrierless or with a very thin liner and so keeps more of the cross section conducting.
ULK: Ultra Low-k: The most aggressive low-k dielectrics, typically porous carbon-doped oxides with k below about 2.5.

Modelling and simulation

TCAD: Technology Computer-Aided DesignIn depth: Technology computer-aided design (TCAD): software that simulates semiconductor fabrication steps and the electrical behaviour of the resulting devices from physics.

Node and scaling

Cell height: The vertical size of a standard cell, usually quoted in routing tracks, for example a 6-track or 5-track library.
CPP: Contacted Poly Pitch: The centre-to-centre distance between adjacent transistor gates including the contact between them, the fundamental horizontal scaling dimension in the front end.
Dennard scaling: The 1974 scaling rule that shrinking a transistor's dimensions and voltage together keeps power density constant, so each node gave more transistors at the same power.
Equivalent node: A way of comparing processes from different vendors by asking which named node their density and performance actually match.
Fin depopulation: Reducing the number of fins per standard cell from one node to the next, for example from three fins to two, to shrink cell height and raise density.
Fin pitch: The centre-to-centre spacing between adjacent fins in a FinFET process, a key scaling dimension alongside gate pitch and metal pitch.
HVM: High Volume Manufacturing: The stage at which a process is fully qualified and running production wafers at scale with stable yield.
Leading edge nodeIn depth: The most advanced process generation in production or ramping, currently the 3 nm and 2 nm classes, with the 2 nm class now in volume production.
Mature node: A process generation whose equipment is fully depreciated and whose yields are stable, typically 28 nm and above.
MMP: Minimum Metal Pitch: The tightest centre-to-centre spacing of lines in the densest interconnect layer of a process.
Moore's Law: Gordon Moore's 1965 observation, revised in 1975, that the number of components on an economically optimal integrated circuit doubles roughly every two years.
More than Moore: Adding value by integrating non-digital functions such as sensors, RF, power and analog, or by advanced packaging, rather than by shrinking logic.
Risk productionIn depth: The stage where a foundry accepts customer wafers on a new node around the time of full reliability qualification, sometimes shortly before it, with yield and parameters still moving.
Technology node: The label a foundry gives a generation of process technology, such as 7 nm or N2.
Transistor density: The number of transistors that fit in a square millimetre, usually quoted in millions of transistors per mm2.

Power delivery and 3D

3D scaling: Pursuing density by building upward, through stacked devices, stacked wafers or stacked packages, rather than by shrinking features laterally.
BPR: Buried Power Rail: A power rail sunk into the substrate below the transistors instead of running in the lowest metal layers.
BSPDN: Backside Power Delivery NetworkIn depth: Routing power and ground on the back of the thinned wafer and connecting up to the transistors through nano-scale through-silicon vias.
Monolithic 3D: Building a second tier of transistors directly on top of a finished first tier on the same wafer, connected by ordinary nano-scale vias rather than bonded interfaces.
nTSV: Nano Through-Silicon Via: A very fine through-silicon via, on the order of a hundred nanometres or less, used to connect backside power metal to buried rails or device contacts.
PowerVia: Intel's backside power delivery implementation, in which power reaches the cell through vias from the wafer's back side rather than through the frontside metal stack.
Super Power Rail: TSMC's backside power delivery scheme, announced for its A16 node, which connects the backside power network directly to the transistor source and drain contacts.

Process flow

FEOL: Front End Of Line: The portion of wafer fabrication that builds the transistors themselves, covering isolation, wells, gates, spacers, source/drain epitaxy and implants.
MEOL: Middle End Of Line: The steps that connect transistors to the first metal layer, including silicide, trench contacts, gate contacts and the lowest vias.
Technology transferIn depth: Moving a process, product or test flow from one site, fab or partner to another, with its recipes, specifications, equipment settings and know-how, and proving that the receiving site matches the o...
Thermal budgetIn depth: The cumulative time-at-temperature a wafer can tolerate before earlier structures are damaged or dopant profiles smear.

Specialty processes

BCD: Bipolar-CMOS-DMOS: A process that integrates bipolar devices for precision analog, CMOS for logic and DMOS transistors for power switching on one die.
BiCMOS: Bipolar CMOS: A process combining bipolar junction transistors with CMOS on the same die, using the bipolar devices where high gain, good matching or high drive is needed.
eFlash: Embedded flash: Non-volatile flash memory integrated on the same die as logic, used for microcontroller code storage and for trim and calibration data.
eMRAM: Embedded Magnetoresistive Random Access Memory: Non-volatile memory embedded in the BEOL using magnetic tunnel junctions, offered as an eFlash replacement at 28 nm and below.
RF CMOS: Radio Frequency CMOS: A CMOS process tuned for radio circuits, adding high-Q inductors, thick top metal, precision capacitors, varactors and accurate high frequency device models.
RF SOI: Radio Frequency Silicon On Insulator: An SOI process on a high-resistivity substrate used for antenna switches, tuners and low noise amplifiers in mobile front-end modules.
SiGe BiCMOS: Silicon Germanium Bipolar CMOS: A BiCMOS process whose bipolar devices are silicon-germanium heterojunction bipolar transistors, offering very high cutoff frequency and low noise.
Specialty process: A process optimised for a function other than dense digital logic, such as power, RF, analog, display driver, MEMS or image sensing.

Substrates and wafers

200 mm wafer: The 200 millimetre wafer size that dominates mature and specialty manufacturing, including analog, power, MEMS and many microcontrollers.
300 mm wafer: The 300 millimetre diameter silicon wafer that is the standard substrate for leading-edge logic and memory.
450 mm wafer: A proposed 450 millimetre wafer generation that was studied intensively around 2010 but never reached production.
BOX: Buried Oxide: The buried silicon dioxide layer that separates the active silicon film from the handle wafer in an SOI substrate.
Bulk CMOS: The standard process built directly on a solid silicon wafer, with devices isolated by wells and shallow trenches rather than a buried oxide.
Czochralski process: The method for growing monocrystalline silicon ingots by dipping a seed crystal into molten silicon and slowly pulling while rotating.
Smart Cut: Soitec's layer transfer process that implants hydrogen to create a cleave plane, bonds the wafer to a handle, and splits off a thin, uniform silicon film.
SOI: Silicon On Insulator: A substrate in which a thin device-quality silicon layer sits on a buried oxide over the handle wafer.

Transistor architecture

Back-bias: Applying a voltage to a well or back gate beneath the channel to shift threshold voltage at runtime.
CFET: Complementary Field Effect Transistor: A device that stacks the n-channel transistor directly above the p-channel transistor instead of placing them side by side, collapsing a CMOS pair into one footprint.
FD-SOI: Fully Depleted Silicon On Insulator: An SOI flavour whose silicon film is thin enough that the channel is entirely depleted with no body doping.
FinFET: Fin Field Effect TransistorIn depth: A transistor whose channel is a thin vertical silicon fin wrapped by the gate on three sides, giving far better electrostatic control than a planar device.
Forksheet: A nanosheet variant in which a dielectric wall separates the n-device and p-device sheets, letting the n-to-p spacing shrink below what a free-standing gate needs.
GAA: Gate-All-AroundIn depth: A transistor architecture in which the gate completely surrounds the channel on all sides, giving the best electrostatic control and the steepest subthreshold behaviour.
MBCFET: Multi-Bridge Channel Field Effect Transistor: Samsung's trade name for its stacked nanosheet gate-all-around transistor, used from its 3 nm class process onward.
NanosheetIn depth: The mainstream gate-all-around device, built from a vertical stack of wide, thin horizontal silicon sheets each fully wrapped by the gate.
Nanowire: A gate-all-around channel with a narrow, roughly square or circular cross section.
PD-SOI: Partially Depleted Silicon On Insulator: An SOI flavour with a silicon film thick enough that part of the body stays neutral and electrically floating.
Planar transistor: The classical MOSFET geometry in which a flat gate sits on top of a flat channel and controls it from one side only.
RibbonFET: Intel's brand name for its gate-all-around nanosheet transistor, introduced with the Intel 18A node.

Variation and DTCO

DTCO: Design Technology Co-OptimizationIn depth: Developing the process and the standard cell and design rules together, so that density and performance gains come from layout choices as much as from lithographic shrink.
Process variationIn depth: The spread in device and interconnect parameters caused by imperfect control of doping, film thickness, patterning and etch.
RDF: Random Dopant Fluctuation: Device-to-device threshold voltage mismatch caused by the statistically small and randomly placed number of dopant atoms in a tiny channel.
STCO: System Technology Co-Optimization: Extending co-optimisation up to the system level, deciding how to partition a design across chiplets, memory tiers, packaging and process nodes.

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